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[209.132.180.67]) by mx.google.com with ESMTP id w33-v6si2210056plb.470.2018.04.10.02.59.31; Tue, 10 Apr 2018 03:00:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752751AbeDJJ4M (ORCPT + 99 others); Tue, 10 Apr 2018 05:56:12 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:35940 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752491AbeDJJ4L (ORCPT ); Tue, 10 Apr 2018 05:56:11 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E63391435; Tue, 10 Apr 2018 02:56:10 -0700 (PDT) Received: from e107981-ln.cambridge.arm.com (e107981-ln.cambridge.arm.com [10.1.207.54]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C07A63F487; Tue, 10 Apr 2018 02:56:08 -0700 (PDT) Date: Tue, 10 Apr 2018 10:56:02 +0100 From: Lorenzo Pieralisi To: Gustavo Pimentel Cc: "bhelgaas@google.com" , "Joao.Pinto@synopsys.com" , "jingoohan1@gmail.com" , "kishon@ti.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "linux-pci@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" Subject: Re: [PATCH v2 6/9] PCI: dwc: Define maximum number of vectors Message-ID: <20180410095602.GA27363@e107981-ln.cambridge.arm.com> References: <20180409160356.GA14533@e107981-ln.cambridge.arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Apr 10, 2018 at 08:59:30AM +0100, Gustavo Pimentel wrote: > Hi Lorenzo, > > On 09/04/2018 17:03, Lorenzo Pieralisi wrote: > > On Mon, Apr 09, 2018 at 10:41:15AM +0100, Gustavo Pimentel wrote: > >> Adds a callback that defines the maximum number of vectors that can be use > >> by the Root Complex. > >> > >> Since this is a parameter associated to each SoC IP setting, makes sense to > >> be configurable and easily visible to future modifications. > >> > >> The designware IP supports a maximum of 256 vectors. > > > > I think that a DT property instead of a callback would have made more > > sense - I struggle to see the point in defining a callback to initialize > > a variable, this can be done in the generic dwc code (and a DT binding). > > The addition of this callback was done in MSI-X patch series before I take over > the PCIe Designware driver responsibility. However I remember a thread in which > this subject was discussed (see [1]), maybe this could bring some light about > the motive why is was done like this. If you don't agree I can do patch after > this series only focusing on this topic in order to do like to suggested. > > [1] -> https://www.spinics.net/lists/linux-pci/msg61835.html Lucas has a point - it is fine to handle them as you do in this patch, it does not make much sense to add a property for something that strictly depends on the compatible string. Thanks, Lorenzo