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[209.132.180.67]) by mx.google.com with ESMTP id u8-v6si2436594plh.469.2018.04.10.04.18.14; Tue, 10 Apr 2018 04:18:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752755AbeDJLPO (ORCPT + 99 others); Tue, 10 Apr 2018 07:15:14 -0400 Received: from mga04.intel.com ([192.55.52.120]:61226 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752323AbeDJLPM (ORCPT ); Tue, 10 Apr 2018 07:15:12 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Apr 2018 04:15:12 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.48,431,1517904000"; d="scan'208";a="190279974" Received: from ahunter-desktop.fi.intel.com (HELO [10.237.72.168]) ([10.237.72.168]) by orsmga004.jf.intel.com with ESMTP; 10 Apr 2018 04:15:10 -0700 Subject: Re: [4.9, 1/1] mmc: sdhci-dwc-mshc-pci: synopsys dwc mshc support To: Prabu Thangamuthu , Ulf Hansson , "linux-kernel@vger.kernel.org" , "linux-mmc@vger.kernel.org" Cc: Manjunath M Bettegowda References: <705D14B1C7978B40A723277C067CEDE2010A99681A@IN01WEMBXB.internal.synopsys.com> From: Adrian Hunter Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Message-ID: Date: Tue, 10 Apr 2018 14:14:13 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 MIME-Version: 1.0 In-Reply-To: <705D14B1C7978B40A723277C067CEDE2010A99681A@IN01WEMBXB.internal.synopsys.com> Content-Type: text/plain; charset=windows-1252 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Not sure what is going on this this patch. Apart from the mangled mail, it is not clear it is intended for upstream? Regards Adrian On 28/03/18 18:28, Prabu Thangamuthu wrote: > Synopsys DWC MSHC IP is complaint to SD Standard Host Controller Interface > > specification. This patch is to enable DWC MSHC controller on HPAS-DX > > platform connected using PCIe interface. > > ? > > As clock generation logic is implemented in MMCM block of HAPS-DX platform, > > we need separate functions to control the MMCM module to generate required > > clocks with respect to the mode of operation. Also we have the platform > > specific set_power function to support different VDD's of eMMC device. > > ? > > Signed-off-by: Prabu Thangamuthu > > --- > > MAINTAINERS?????????????????????????? |?? 7 ++ > > drivers/mmc/host/Makefile???????????? |?? 3 +- > > drivers/mmc/host/sdhci-dwc-mshc-pci.c | 137 ++++++++++++++++++++++++++++++++++ > > drivers/mmc/host/sdhci-dwc-mshc-pci.h |? 44 +++++++++++ > > drivers/mmc/host/sdhci-pci-core.c???? |? 25 +++++++ > > 5 files changed, 215 insertions(+), 1 deletion(-) > > create mode 100644 drivers/mmc/host/sdhci-dwc-mshc-pci.c > > create mode 100644 drivers/mmc/host/sdhci-dwc-mshc-pci.h > > ? > > diff --git a/MAINTAINERS b/MAINTAINERS > > index 63cefa6..869b92b 100644 > > --- a/MAINTAINERS > > +++ b/MAINTAINERS > > @@ -10808,6 +10808,13 @@ S:??????????????? Maintained > > F:?????????? drivers/mmc/host/sdhci* > > F:?????????? include/linux/mmc/sdhci* > > +SYNOPSYS SDHCI COMPLIANT DWC MSHC DRIVER > > +M:??????? Prabu Thangamuthu > > +M:??????? Manjunath M B > > +L:????????? linux-mmc@vger.kernel.org > > +S:????????? Maintained > > +F:????????? drivers/mmc/host/sdhci-dwc* > > + > > SECURE COMPUTING > > M:???????? Kees Cook > > R:?????????? Andy Lutomirski > > diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile > > index e2bdaaf4..e83355f 100644 > > --- a/drivers/mmc/host/Makefile > > +++ b/drivers/mmc/host/Makefile > > @@ -9,7 +9,8 @@ obj-$(CONFIG_MMC_MXC)?????????????????? += mxcmmc.o > > obj-$(CONFIG_MMC_MXS)??????????????????????? += mxs-mmc.o > > obj-$(CONFIG_MMC_SDHCI)???????????????????? += sdhci.o > > obj-$(CONFIG_MMC_SDHCI_PCI)??????????? += sdhci-pci.o > > -sdhci-pci-y???????????????????????????????????????? += sdhci-pci-core.o > sdhci-pci-o2micro.o > > +sdhci-pci-y??????????????????????????????????????? += sdhci-pci-core.o > sdhci-pci-o2micro.o \ > > +???????????????????????????????????????????????????????????? ?? > sdhci-dwc-mshc-pci.o > > obj-$(subst m,y,$(CONFIG_MMC_SDHCI_PCI))?? += sdhci-pci-data.o > > obj-$(CONFIG_MMC_SDHCI_ACPI)???????? += sdhci-acpi.o > > obj-$(CONFIG_MMC_SDHCI_PXAV3)???? += sdhci-pxav3.o > > diff --git a/drivers/mmc/host/sdhci-dwc-mshc-pci.c > b/drivers/mmc/host/sdhci-dwc-mshc-pci.c > > new file mode 100644 > > index 0000000..2f91ef7 > > --- /dev/null > > +++ b/drivers/mmc/host/sdhci-dwc-mshc-pci.c > > @@ -0,0 +1,137 @@ > > +/* > > + * SDHCI driver for Synopsys DWC_MSHC controller > > + * > > + * Copyright (C) 2017-2018 Synopsys, Inc. (www.synopsys.com) > > + * > > + * Authors: > > + *????????? Prabu Thangamuthu > > + *????????? Manjunath M B > > + * > > + * This program is free software; you can redistribute it and/or modify > > + * it under the terms of the GNU General Public License version 2 as > > + * published by the Free Software Foundation. > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > + > > +#include "sdhci.h" > > +#include "sdhci-pci.h" > > +#include "sdhci-dwc-mshc-pci.h" > > + > > +#define DRIVER_NAME "sdhci_snps" > > + > > +/* Default emmc vdd is set to 1.8V */ > > +static unsigned int emmc_vdd = SDHC_EMMC_VDD_180V; > > +module_param(emmc_vdd, int, 0444); > > + > > +void sdhci_snps_set_clock(struct sdhci_host *host, unsigned int clock) > > +{ > > +???????????? u16 clk = 0; > > +???????????? u32 reg = 0; > > +???????????? u32 vendor_ptr = 0; > > + > > +???????????? vendor_ptr = sdhci_readw(host, SDHCI_VENDOR_PTR_R); > > + > > +???????????? /* Disable Software managed rx tuning */ > > +???????????? reg = sdhci_readl(host, (SDHC_AT_CTRL_R + vendor_ptr)); > > +???????????? reg &= ~SDHC_SW_TUNE_EN; > > +???????????? sdhci_writel(host, reg, (SDHC_AT_CTRL_R + vendor_ptr)); > > + > > +???????????? if (clock <= 52000000) { > > +???????????????????????????? sdhci_set_clock(host, clock); > > +???????????? } else { > > +???????????????????????????? /* Assert reset to MMCM */ > > +???????????????????????????? reg = sdhci_readl(host, (SDHC_GPIO_OUT + > vendor_ptr)); > > +???????????????????????????? reg |= SDHC_CCLK_MMCM_RST; > > +???????????????????????????? sdhci_writel(host, reg, (SDHC_GPIO_OUT + > vendor_ptr)); > > + > > +???????????????????????????? /* Configure MMCM*/ > > +???????????????????????????? sdhci_writel(host, DIV_REG_100_MHZ, > SDHC_MMCM_DIV_REG); > > +???????????????????????????? sdhci_writel(host, CLKFBOUT_100_MHZ, > > +???????????????????????????????????????????????????????????? > SDHC_MMCM_CLKFBOUT); > > + > > +???????????????????????????? /* De-assert reset to MMCM*/ > > +???????????????????????????? reg = sdhci_readl(host, (SDHC_GPIO_OUT + > vendor_ptr)); > > +???????????????????????????? reg &= ~SDHC_CCLK_MMCM_RST; > > +???????????????????????????? sdhci_writel(host, reg, (SDHC_GPIO_OUT + > vendor_ptr)); > > + > > +???????????????????????????? /* Enable clock */ > > +???????????????????????????? clk = SDHCI_PROG_CLOCK_MODE | SDHCI_CLOCK_INT_EN | > > +???????????????????????????????????????????? SDHCI_CLOCK_CARD_EN; > > +???????????????????????????? sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); > > +???????????? } > > +} > > +EXPORT_SYMBOL_GPL(sdhci_snps_set_clock); > > + > > +void sdhci_snps_set_power(struct sdhci_host *host, unsigned char mode, > > +???????????????????????????? ? ???unsigned short vdd) > > +{ > > +???????????? u8 pwr = 0; > > +???????????? u16 ctrl; > > + > > +???????????? if (mode != MMC_POWER_OFF) { > > +???????????????????????????? switch (1 << vdd) { > > +???????????????????????????? case MMC_VDD_165_195: > > +???????????????????????????????????????????? pwr = SDHCI_POWER_180; > > +???????????????????????????????????????????? break; > > +???????????????????????????? case MMC_VDD_29_30: > > +???????????????????????????? case MMC_VDD_30_31: > > +???????????????????????????????????????????? pwr = SDHCI_POWER_300; > > +???????????????????????????????????????????? break; > > +???????????????????????????? case MMC_VDD_32_33: > > +???????????????????????????? case MMC_VDD_33_34: > > +???????????????????????????????????????????? pwr = SDHCI_POWER_330; > > +???????????????????????????????????????????? break; > > +???????????????????????????? default: > > +???????????????????????????????????????????? WARN(1, "%s: Invalid vdd %#x\n", > > +???????????????????????????????????????????? ???? mmc_hostname(host->mmc), > vdd); > > +???????????????????????????????????????????? break; > > +???????????????????????????? } > > +???????????? } > > + > > +???????????? if (host->pwr == pwr) > > +???????????????????????????? return; > > + > > +???????????? host->pwr = pwr; > > + > > +???????????? if (pwr == 0) { > > +???????????????????????????? sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); > > +???????????? } else { > > +???????????????????????????? sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); > > + > > +???????????????????????????? /* > > +???????????????????????????? * Enable it for eMMC phy cfg1 test with 1.8V mode > > +???????????????????????????? */ > > +???????????????????????????? if (emmc_vdd == SDHC_EMMC_VDD_180V) { > > +???????????????????????????????????????????? pwr = SDHCI_POWER_180; > > +???????????????????????????????????????????? sdhci_writeb(host, pwr, > SDHCI_POWER_CONTROL); > > + > > +???????????????????????????????????????????? ctrl = sdhci_readw(host, > SDHCI_HOST_CONTROL2); > > +???????????????????????????????????????????? /* > > +???????????????????????????????????????????? * Enable 1.8V Signal Enable in > the Host Control2 > > +???????????????????????????????????????????? * register > > +???????????????????????????????????????????? */ > > +???????????????????????????????????????????? ctrl |= SDHCI_CTRL_VDD_180; > > +???????????????????????????????????????????? sdhci_writew(host, ctrl, > SDHCI_HOST_CONTROL2); > > +???????????????????????????? } > > +???????????????????????????? pwr |= SDHCI_POWER_ON; > > + > > +???????????????????????????? sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); > > +???????????? } > > +} > > +EXPORT_SYMBOL_GPL(sdhci_snps_set_power); > > + > > +int sdhci_snps_pci_probe_slot(struct sdhci_pci_slot *slot) > > +{ > > +???????????? slot->host->caps = sdhci_readl(host, SDHCI_CAPABILITIES); > > +???????????? slot->host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); > > + > > +???????????? return 0; > > +} > > +EXPORT_SYMBOL_GPL(sdhci_snps_pci_probe_slot); > > + > > +MODULE_PARM_DESC(emmc_vdd, "VDD to configure eMMC device supply voltage"); > > + > > diff --git a/drivers/mmc/host/sdhci-dwc-mshc-pci.h > b/drivers/mmc/host/sdhci-dwc-mshc-pci.h > > new file mode 100644 > > index 0000000..97f5529 > > --- /dev/null > > +++ b/drivers/mmc/host/sdhci-dwc-mshc-pci.h > > @@ -0,0 +1,44 @@ > > +/* > > + * SDHCI driver for Synopsys DWC_MSHC controller > > + * > > + * Copyright (C) 2017-2018 Synopsys, Inc. (www.synopsys.com) > > + * > > + * Authors: > > + *????????? Prabu Thangamuthu > > + *????????? Manjunath M B > > + * > > + * This program is free software; you can redistribute it and/or modify > > + * it under the terms of the GNU General Public License version 2 as > > + * published by the Free Software Foundation. > > + */ > > + > > +#ifndef __SDHCI_DWC_MSHC_PCI_H__ > > +#define __SDHCI_DWC_MSHC_PCI_H__ > > + > > +#define SDHCI_VENDOR_PTR_R???????????????????????????? ?????? 0xE8 > > + > > +/* Module Parameters */ > > +#define SDHC_EMMC_VDD_330V????????????????????????? ?????? 33 > > +#define SDHC_EMMC_VDD_180V????????????????????????? ?????? 18 > > + > > +/* Synopsys Vendor Specific Registers */ > > +#define SDHC_GPIO_OUT????????????????????????? 0x34 > > +#define SDHC_AT_CTRL_R???????????????????????????????????????? ?????? 0x40 > > + > > +#define SDHC_SW_TUNE_EN?????????????????????????????????? ?????? 0x00000010 > > + > > +/* MMCM DRP */ > > +#define SDHC_MMCM_DIV_REG??????????????????????????? ?????? 0x1020 > > +#define DIV_REG_100_MHZ???????????????????????????????????? ?????? 0x1145 > > + > > +#define SDHC_MMCM_CLKFBOUT???????????????????????? ?????? 0x1024 > > +#define CLKFBOUT_100_MHZ????????????????? ?????? 0x0000 > > + > > +#define SDHC_CCLK_MMCM_RST????????????????????????? ?????? 0x00000001 > > + > > +int sdhci_snps_pci_probe_slot(struct sdhci_pci_slot *slot); > > +void sdhci_snps_set_clock(struct sdhci_host *host, unsigned int clock); > > +void sdhci_snps_set_power(struct sdhci_host *host, unsigned char mode, > > +???????????????????????????? ???? unsigned short vdd); > > + > > +#endif > > diff --git a/drivers/mmc/host/sdhci-pci-core.c > b/drivers/mmc/host/sdhci-pci-core.c > > index b0b9ceb..f16ae5b 100644 > > --- a/drivers/mmc/host/sdhci-pci-core.c > > +++ b/drivers/mmc/host/sdhci-pci-core.c > > @@ -31,6 +31,7 @@ > > #include "sdhci.h" > > #include "sdhci-pci.h" > > #include "sdhci-pci-o2micro.h" > > +#include "sdhci-dwc-mshc-pci.h" > > ?static int sdhci_pci_enable_dma(struct sdhci_host *host); > > static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width); > > @@ -79,6 +80,23 @@ static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) > > ?????????????? return 0; > > } > > +/* Synopsys DWC MSHC Controller based on SDHCI-PCI */ > > +static const struct sdhci_ops sdhci_snps_ops = { > > +???????????? .set_clock??????????? = sdhci_snps_set_clock, > > +???????????? .set_power???????? = sdhci_snps_set_power, > > +???????????? .enable_dma???? = sdhci_pci_enable_dma, > > +???????????? .set_bus_width = sdhci_pci_set_bus_width, > > +???????????? .reset??????????????????? = sdhci_reset, > > +???????????? .set_uhs_signaling = sdhci_set_uhs_signaling, > > +???????????? .hw_reset?????????????????????????? = sdhci_pci_hw_reset, > > +???????????? .select_drive_strength? = sdhci_pci_select_drive_strength, > > +}; > > + > > +static const struct sdhci_pci_fixes sdhci_snps = { > > +???????????? .probe_slot??????? = sdhci_snps_pci_probe_slot, > > +???????????? .ops?????????????????????? = &sdhci_snps_ops, > > +}; > > + > > static const struct sdhci_pci_fixes sdhci_ricoh = { > > ?????????????? .probe????????????????? = ricoh_probe, > > ?????????????? .quirks????????????????? = SDHCI_QUIRK_32BIT_DMA_ADDR | > > @@ -857,6 +875,13 @@ static int amd_probe(struct sdhci_pci_chip *chip) > > ?static const struct pci_device_id pci_ids[] = { > > ?????????????? { > > +???????????????????????????? .vendor??????????????? = 0x16c3,???????????? > /* Synopsys Vendor ID */ > > +???????????????????????????? .device???????????????? = 0xc202,???????????? > /* IPK HAPS_Dx */ > > +???????????????????????????? .subvendor???????? = PCI_ANY_ID, > > +???????????????????????????? .subdevice????????? = PCI_ANY_ID, > > +???????????????????????????? .driver_data?????? = (kernel_ulong_t)&sdhci_snps, > > +???????????? }, > > +???????????? { > > ?????????????????????????????? .vendor??????????????? = PCI_VENDOR_ID_RICOH, > > ?????????????????????????????? .device???????????????? = > PCI_DEVICE_ID_RICOH_R5C822, > > ?????????????????????????????? .subvendor???????? = PCI_ANY_ID, > > -- > > 1.9.1 > > ? >