Received: by 10.213.65.68 with SMTP id h4csp3872364imn; Tue, 10 Apr 2018 06:03:52 -0700 (PDT) X-Google-Smtp-Source: AIpwx48kVxEaj+2pkaV2fYkXwyRfx5jfndhKooresvXyr+xwVBNv8Q2p+ownkJ11ntYMqwqRkGTO X-Received: by 2002:a17:902:529:: with SMTP id 38-v6mr390621plf.64.1523365431977; Tue, 10 Apr 2018 06:03:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1523365431; cv=none; d=google.com; s=arc-20160816; b=k6kEClGNucKwjc/CAIp2GTSctQnN02JxE5DZZwb3ACLnAXuRM5x/i0madgwCDnUtND omFJb+oa3mQDvDywTtuQOMlAYRGPfGyr8LoA6WnMDZjERAEDJZq+wj1fQcapjxKfIrhi oqw0wL23JHkeqFq6YjU8n3Q9gn45ZLkpNUdDnR2r5P06+vXSOTAcBrjymwJbjHgkiTjd ZUSU/7rV1I31XamFCX/MLW0oR6pS2fYHfuBFrvQlYl2Ki+7qaC3yXUMKZjhbT5CWpCQK 9Y4Re0el2FQcxqo3u4diiy/B45CGJYe4IEj3o0VW6lm8n5vP5nSTPDIVwTG2frqTV8qu kZpg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=HW61Q5w7QUvSoG+HNFc4E4bAauRkwBEp6VEsRKCxbys=; b=QaDnW3REkd8vU2+vV4sa43ztXbvOUQhSyzNxCeyCIdox9F2UUOME6TLXjLUat0fGur CLCvlk2JQBqpQgl+KxDtCZ5mHq6qQryopMcsBntmsH1QwlAUQtPvt7t8aWDe3FJWIbmC W1zEq04eunGsSzyebSahuKc+SGYixtQdGzhrTPtEu2FONuSkuJTjH/k9WrR94iTMqVVc BL6CqelpQ2q6Ese3mSH5oIxYml+YdEtynbk6GpKYzT/d4zfg2CQftUSUupy3ZF62xl8o wFsyeIA3f+6CI4+PogVH4nNPdnOZz4c4jPQSxR2+NSbaDaJu2a3hHX69D1ayPlWVsfGI O1bA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=synopsys.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f2-v6si2594780plo.434.2018.04.10.06.03.14; Tue, 10 Apr 2018 06:03:51 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=synopsys.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753654AbeDJM7D (ORCPT + 99 others); Tue, 10 Apr 2018 08:59:03 -0400 Received: from smtprelay2.synopsys.com ([198.182.60.111]:54196 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753198AbeDJM6v (ORCPT ); Tue, 10 Apr 2018 08:58:51 -0400 Received: from mailhost.synopsys.com (mailhost1.synopsys.com [10.12.238.239]) by smtprelay.synopsys.com (Postfix) with ESMTP id 2A19710C0DAC; Tue, 10 Apr 2018 05:58:51 -0700 (PDT) Received: from pt02.synopsys.com (pt02.internal.synopsys.com [10.107.23.240]) by mailhost.synopsys.com (Postfix) with ESMTP id DA7B55359; Tue, 10 Apr 2018 05:58:50 -0700 (PDT) Received: from UbuntuMate-64Bits.internal.synopsys.com (gustavo-e7480.internal.synopsys.com [10.107.25.102]) by pt02.synopsys.com (Postfix) with ESMTP id 8BC003E53B; Tue, 10 Apr 2018 13:58:49 +0100 (WEST) From: Gustavo Pimentel To: bhelgaas@google.com, lorenzo.pieralisi@arm.com, Joao.Pinto@synopsys.com, jingoohan1@gmail.com, kishon@ti.com, robh+dt@kernel.org, mark.rutland@arm.com Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, gustavo.pimentel@synopsys.com Subject: [PATCH v3 07/10] PCI: dwc: Define maximum number of vectors Date: Tue, 10 Apr 2018 13:58:39 +0100 Message-Id: <04c2a7739be0a211e2123c54bf55368624a3ecd1.1523360166.git.gustavo.pimentel@synopsys.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Adds a callback that defines the maximum number of vectors that can be use by the Root Complex. Since this is a parameter associated to each SoC IP setting, makes sense to be configurable and easily visible to future modifications. The designware IP supports a maximum of 256 vectors. Signed-off-by: Gustavo Pimentel --- Change v1->v2: - Nothing changed, just to follow the patch set version. Change v2->v3: - Nothing changed, just to follow the patch set version. drivers/pci/dwc/pcie-designware-plat.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/pci/dwc/pcie-designware-plat.c b/drivers/pci/dwc/pcie-designware-plat.c index 4be9c3a..04afa80 100644 --- a/drivers/pci/dwc/pcie-designware-plat.c +++ b/drivers/pci/dwc/pcie-designware-plat.c @@ -48,8 +48,14 @@ static int dw_plat_pcie_host_init(struct pcie_port *pp) return 0; } +static void dw_plat_set_num_vectors(struct pcie_port *pp) +{ + pp->num_vectors = MAX_MSI_IRQS; +} + static const struct dw_pcie_host_ops dw_plat_pcie_host_ops = { .host_init = dw_plat_pcie_host_init, + .set_num_vectors = dw_plat_set_num_vectors, }; static int dw_plat_pcie_establish_link(struct dw_pcie *pci) -- 2.7.4