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[209.132.180.67]) by mx.google.com with ESMTP id 73si2500047pfz.20.2018.04.10.11.10.04; Tue, 10 Apr 2018 11:10:41 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=BaLfJ1q5; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752191AbeDJSGp (ORCPT + 99 others); Tue, 10 Apr 2018 14:06:45 -0400 Received: from mail-qk0-f171.google.com ([209.85.220.171]:39636 "EHLO mail-qk0-f171.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751803AbeDJSGn (ORCPT ); Tue, 10 Apr 2018 14:06:43 -0400 Received: by mail-qk0-f171.google.com with SMTP id j73so14361589qke.6; Tue, 10 Apr 2018 11:06:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=J97ejZD/YVt7RmQFUtoKkNkX1RaOjlhJgyPXaTxwxko=; b=BaLfJ1q5PNSMRsOKJstRgqUxx2JsZCY3ob0I6vVeMmP54X5Y/yJ8gNcf7LtZZJykr7 a3ZuYqTy+kVq9Tccsdi7ZkClkewBW5qzIAR0VSwALA4wM1colWS8mvnf+ioy26yHaaDL 0AAa89qwJxWqrWvTOt7loX8cxinGYWryen8+aKCAkCMSluD6ZOqDpiC1ULDITSgKrXxs LjaD5HjDkg5nYCK5uUzC3wTVixyX1GS9ETVSN7FgyBiJfFam2n5m+kb1l7DH4VrW0HAz NDTTxJgCeDr7FJoXDZ3J8YGEe3K6KXL2r4geLzZq89QK/OfDRcqkgiR7X98nZQxdZV1L tFhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=J97ejZD/YVt7RmQFUtoKkNkX1RaOjlhJgyPXaTxwxko=; b=IB9wbl38NVgIG7X08NijXNSGLkMUS0q8+J32J6++xXqOZAkG+ECsRNd5FqBwwJhAer pEFvufnq/rBLb0odd4Q6oqF8zxp6doeXwN1DXQITgx5TJro4dVV+UWue/4kKBjTAuzba 2WWEXdH9NoabbZUZgPyvYhKeN1pwaWvRyZhsQy+sWNGbKIBOKAqRkfZ7QU/5uG8oYMq/ kNymSnICUXbH25/+ZxSPeu2lXfRNUP1m6wWmfU4GFel6YUjCZN7yUbjMo5xLVzVCKPTF KZOz5V04KsbasoqtarYUzDfgWtozY2S7Oj6jHcIDF4i7LNbETWioQAkk3tqEaHmNgB9H WXdA== X-Gm-Message-State: ALQs6tBsbwy8z6o9vdL2Q4gqXyUiGXNAxuhwSnACOJw43t2zoxvsNdDK 0/ZzsUlbWY03z2FnI9QhCMjDFmIV8CJRrFPenNs= X-Received: by 10.55.47.194 with SMTP id v185mr2132423qkh.301.1523383602206; Tue, 10 Apr 2018 11:06:42 -0700 (PDT) MIME-Version: 1.0 Received: by 10.12.137.74 with HTTP; Tue, 10 Apr 2018 11:06:41 -0700 (PDT) In-Reply-To: <0e9bea79eae7504e61fabdb4a0311f8fdc2f6b25.1523376423.git.hns@goldelico.com> References: <0e9bea79eae7504e61fabdb4a0311f8fdc2f6b25.1523376423.git.hns@goldelico.com> From: Andy Shevchenko Date: Tue, 10 Apr 2018 21:06:41 +0300 Message-ID: Subject: Re: [PATCH v3 2/4] gpio: pca953x: add register definitions for pcal6524 and fix address calculation To: "H. Nikolaus Schaller" Cc: Kumar Gala , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Linus Walleij , Alexandre Courbot , devicetree , "open list:GPIO SUBSYSTEM" , Linux Kernel Mailing List , Discussions about the Letux Kernel , kernel@pyra-handheld.com Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Apr 10, 2018 at 7:07 PM, H. Nikolaus Schaller wrote: > PCAL chips ("L" seems to stand for "latched") have additional > registers starting at address 0x40 to control the latches, > interrupt mask, pull-up and pull down etc. > > The constants are so far defined in a way that they fit for > the pcal9555a when shifted by the number of banks, i.e. multiplied > by 2. > > Now the pcal6524 has 3 banks which means the relative offset > must be multiplied by 4 which gives a wrong result if not done > carefully, since the base offset is already included in the offset. > > For the basic registers shared with all pca93xx/tca64xx chips > there is no such offset. > > Therefore, we add code to adjust the register number for exended > registers to the 24 bit accessor functions. > > And we add additional register offset constants (not yet used by > the driver code) which are specific to the pcal6524. > First of all, as I said, please split this to two patches. Don't mix the things. > + /* adjust register address for pcal6524 */ > + if (reg >= PCAL953X_OUT_STRENGTH) > + reg -= PCAL953X_OUT_STRENGTH >> 1; > + Give me some days to think about it. -- With Best Regards, Andy Shevchenko