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[209.132.180.67]) by mx.google.com with ESMTP id 1-v6si3292846plj.247.2018.04.10.13.12.19; Tue, 10 Apr 2018 13:12:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=Ct4tldKD; dkim=pass header.i=@codeaurora.org header.s=default header.b=XkDWVBez; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753306AbeDJUJW (ORCPT + 99 others); Tue, 10 Apr 2018 16:09:22 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:37478 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752057AbeDJUJS (ORCPT ); Tue, 10 Apr 2018 16:09:18 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 45DF760C64; Tue, 10 Apr 2018 20:09:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1523390958; bh=hCbGorxGn+T4WAaTdaCKkEdjc7Xs/Z2rUxwuJu4YqeM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ct4tldKDrxPe/s89ue3eaZuUJnqNA9V8IKKTJGu1YFyLcUfXkNzhykmVCFg4pC3OH y8Zml2T1p0D76YWU8D/vkNA5vM9AfDNThAeZje8Cvv11GlWJWyHBmFU/Jnq4wxeyqg dYQti/ir9Awgcfk4JE0bPrzUoAU+HFSe8EL+utf0= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from rishabhb-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: rishabhb@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 47DEF6081C; Tue, 10 Apr 2018 20:09:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1523390957; bh=hCbGorxGn+T4WAaTdaCKkEdjc7Xs/Z2rUxwuJu4YqeM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XkDWVBezXAN/hVunw2uZiYrLdykaCjRJwnqIlJPXsk/MTenylQojbzMQOoQhalJkh hyEMIhgIJqaKJQHwewQEpFcUJ2YFFuzIz4dZ/1Tw499tQ2C9SIc9t/IfqrWu66WpFP P4/fgpYavEdPOIHo6I015VMa/t9hyjBHo32wzCtk= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 47DEF6081C Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=rishabhb@codeaurora.org From: Rishabh Bhatnagar To: linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Cc: linux-arm@lists.infradead.org, linux-kernel@vger.kernel.org, tsoni@codeaurora.org, kyan@codeaurora.org, ckadabi@codeaurora.org, stanimir.varbanov@linaro.org, evgreen@chromium.org, Rishabh Bhatnagar Subject: [PATCH v4 1/2] Documentation: Documentation for qcom, llcc Date: Tue, 10 Apr 2018 13:08:12 -0700 Message-Id: <1523390893-10904-2-git-send-email-rishabhb@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1523390893-10904-1-git-send-email-rishabhb@codeaurora.org> References: <1523390893-10904-1-git-send-email-rishabhb@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Documentation for last level cache controller device tree bindings, client bindings usage examples. Signed-off-by: Channagoud Kadabi Signed-off-by: Rishabh Bhatnagar --- .../devicetree/bindings/arm/msm/qcom,llcc.txt | 58 ++++++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt new file mode 100644 index 0000000..497cf0f --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt @@ -0,0 +1,58 @@ +== Introduction== + +LLCC (Last Level Cache Controller) provides last level of cache memory in SOC, +that can be shared by multiple clients. Clients here are different cores in the +SOC, the idea is to minimize the local caches at the clients and migrate to +common pool of memory + +Properties: +- compatible: + Usage: required + Value type: + Definition: must be "qcom,sdm845-llcc" + +- reg: + Usage: required + Value Type: + Definition: must be addresses and sizes of the LLCC registers + +- #cache-cells: + Usage: required + Value Type: + Definition: Number of cache cells, must be 1 + +- max-slices: + usage: required + Value Type: + Definition: Number of cache slices supported by hardware + +Example: + + llcc: qcom,llcc@1100000 { + compatible = "qcom,sdm845-llcc"; + reg = <0x1100000 0x250000>; + #cache-cells = <1>; + max-slices = <32>; + }; + +== Client == + +Properties: +- cache-slice-names: + Usage: required + Value type: + Definition: A set of names that identify the usecase names of a + client that uses cache slice. These strings are + used to look up the cache slice entries by name. + +- cache-slices: + Usage: required + Value type: + Definition: The tuple has phandle to llcc device as the first + argument and the second argument is the usecase + id of the client. +For Example: + venus { + cache-slice-names = "vidsc0", "vidsc1"; + cache-slices = <&llcc VIDSC0_ID>, <&llcc VIDSC1_ID>; + }; -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project