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[209.132.180.67]) by mx.google.com with ESMTP id x8si7361pgr.301.2018.04.10.18.27.04; Tue, 10 Apr 2018 18:27:41 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752628AbeDKBWk (ORCPT + 99 others); Tue, 10 Apr 2018 21:22:40 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:48428 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1752295AbeDKBWi (ORCPT ); Tue, 10 Apr 2018 21:22:38 -0400 Received: from DGGEMS404-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id B7F1711644DF0; Wed, 11 Apr 2018 09:22:34 +0800 (CST) Received: from [127.0.0.1] (10.177.29.40) by DGGEMS404-HUB.china.huawei.com (10.3.19.204) with Microsoft SMTP Server id 14.3.361.1; Wed, 11 Apr 2018 09:22:29 +0800 Subject: Re: [PATCH v9 5/5] iommu/arm-smmu: Add support for qcom,smmu-v2 variant To: Tomasz Figa References: <20180313085534.11650-1-vivek.gautam@codeaurora.org> <20180313085534.11650-6-vivek.gautam@codeaurora.org> <61d30fff-1bf8-d2c1-bbe9-f93de836ae77@huawei.com> <7d5af071-ef98-8461-3ce9-e84fc0b3956a@codeaurora.org> CC: Vivek Gautam , Mark Rutland , , linux-arm-msm , Will Deacon , "Linux Kernel Mailing List" , "list@263.net:IOMMU DRIVERS" , Joerg Roedel , , From: Yisheng Xie Message-ID: <65a57964-805b-3a38-71a2-0c383af30539@huawei.com> Date: Wed, 11 Apr 2018 09:22:05 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.177.29.40] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Tomasz, On 2018/4/10 21:14, Tomasz Figa wrote: > Hi Yisheng, > > Sorry, I think we missed your question here. > > On Wed, Mar 28, 2018 at 3:12 PM Yisheng Xie wrote: > >> Hi Vivek, > >> On 2018/3/28 12:37, Vivek Gautam wrote: >>> Hi Yisheng >>> >>> >>> On 3/28/2018 6:54 AM, Yisheng Xie wrote: >>>> Hi Vivek, >>>> >>>> On 2018/3/13 16:55, Vivek Gautam wrote: >>>>> +- power-domains: Specifiers for power domains required to be > powered on for >>>>> + the SMMU to operate, as per generic power domain > bindings. >>>>> + >>>> In this patchset, power-domains is not used right? And you just do the > clock gating, >>>> but not power gating, right? >>> >>> We are handling the power-domains too. Please see the example in this > binding doc. > >> I see, but I do not find the point in code of these patchset, do you mean > PMIC(e.g mmcc) >> will gate the power domain of SMMU(e.g. MDSS_GDSC of mmcc) when PMIC > suspend? > > > If respective SoC power domains is registered as a standard genpd PM > domain, then the runtime PM subsystem will take care of power domain > control at runtime suspend and resume. > Get it, thanks for your explain, I should have learned about this. Thanks Yisheng > Best regards, > Tomasz > > . >