Received: by 10.192.165.156 with SMTP id m28csp1485375imm; Wed, 11 Apr 2018 20:59:04 -0700 (PDT) X-Google-Smtp-Source: AIpwx49XovWyHXFALZNni8zkL2Fdg4nZTZTFM2kDZsTJPEpn4QDPP34f8QXcHPsuWSW3PWpVYxZj X-Received: by 10.99.55.68 with SMTP id g4mr5244518pgn.283.1523505544343; Wed, 11 Apr 2018 20:59:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1523505544; cv=none; d=google.com; s=arc-20160816; b=VW+GRsR8g1mwjetzITVKJyYFlbMZW4qg1SLXOi3hiwaUgC19R0jUUkjjnlLv3lwZkk qIm+AqF2+A2TganTbuve/hoz2GZw7lJc6ZsTKfB91p1lL27t660VgDCA08eSmuQtAHDk MaNCTHdXxc9/AUHH1x4Cc+SrZlukK0auSpyFaKcvmUJDymFD70vvIQtT3v9ikaUyv/yU pnInAPgh3z3lgIP4K1pyqJIipynaWNX36wtx2OpvZQCRJ31FVKmCbd9+POAmPcwo5g/7 aM0p4szV4JZoOIFKFmLzb1Y/7maYmrlMfQ4r2FpUlT+6SgglbfvCdQ0zJtaYkA82xkP6 03xw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from:dkim-signature:arc-authentication-results; bh=fyJu7rE8hqLp5ahNsPtdOCjQbBA3Gf2Fb3WhysqiqL0=; b=EGSooyyh1M9WUVRJaIbdg9xLRRoW7meUG9nO0TFeIfLe4f5dgP8Tws1vJEzWCPwDza K39OFL5SViABSPWTPKqZAG65b46YtHNC5pk0M28wS3x683XYd1IfEy1/3S5pSeBy2BPk o+SRz/0XoBnqBOFF9XnycUgHnEeB7hs7oOi+vSIFBQUqcsZdBERqErnAYgzRRFEsqo18 bpIEocbJyWAuyoxsqRZbSRjeVetFEnE7OXiGiSj32/uhyuu6bBVrtlhsDv64uryXhNyk iaZ7hKta66Mje1BSjWijVuGSzCpWZHW0LuPYAAz8LWfyiD0uDNVVYix3ncY/q9q74bZH nKaw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=hjCjnq+3; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s3-v6si2188345plp.682.2018.04.11.20.58.14; Wed, 11 Apr 2018 20:59:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=hjCjnq+3; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752386AbeDLDyt (ORCPT + 99 others); Wed, 11 Apr 2018 23:54:49 -0400 Received: from fllnx209.ext.ti.com ([198.47.19.16]:65094 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751833AbeDLDyr (ORCPT ); Wed, 11 Apr 2018 23:54:47 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id w3C3sVId012042; Wed, 11 Apr 2018 22:54:31 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1523505271; bh=2XVPYFKZKyBRg7JP2ctmxBa4cZUe+2nQXxiT0UQlVNk=; h=From:To:CC:Subject:Date; b=hjCjnq+3iQLi3uJCzYFNlz+1PYaF5PvB+5KLYenbb3xEGHp6rUsB9wQtQw83TIfrZ jDaZ/Z4cM2BAO41qgM52AHJbR4rpfaZa4HMqTFyDZiEcuvwvMkXIBT7nna2KQLzcH/ YOPQg5hdJaRaRWEGYaKZdHC3oVm3py/1RbIPL4aA= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w3C3sV7R007605; Wed, 11 Apr 2018 22:54:31 -0500 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Wed, 11 Apr 2018 22:54:30 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Wed, 11 Apr 2018 22:54:30 -0500 Received: from ula0393675.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w3C3sQph010150; Wed, 11 Apr 2018 22:54:27 -0500 From: Keerthy To: , , CC: , , , , , , , , Subject: [PATCH 00/14] arm: OMAP: AM437X: Save restores patches for rtc mode with DDR In self-refresh Date: Thu, 12 Apr 2018 09:23:45 +0530 Message-ID: <1523505239-16229-1-git-send-email-j-keerthy@ti.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org RTC plus DDR in self-refresh is power a saving mode where in the entire system including the different voltage rails from PMIC are shutdown except the ones feeding on to RTC and DDR. DDR is kept in self-refresh hence the contents are preserved. RTC ALARM2 is connected to PMIC_EN line once we the ALARM2 is triggered we enter the mode with DDR in self-refresh and RTC Ticking. After a predetermined time an RTC ALARM1 triggers waking up the system. The control goes to bootloader. The bootloader then checks RTC scratchpad registers to confirm it was an rtc_only wakeup and follows a different path, configure bare minimal clocks for ddr and then jumps to the resume address in another RTC scratchpad registers and transfers the control to Kernel. Kernel then restores the saved context. This series is a prerequisite for the rtc mode with DDR in self refresh mode for am437x series of SoCs. As all the voltage domains are shut off apart from RTC and DDR is kept in self refresh additional save/restores are needed. The series applies cleanly against linux-next branch. This mode works only with u-boot built with am43xx_evm_rtconly_defconfig Dave Gerlach (5): memory: ti-emif-sram: Add resume function to recopy sram code ARM: OMAP2+: omap_hwmod: Introduce HWMOD_NEEDS_REIDLE gpio: omap: Restore power_mode configuration at resume time ARM: hwmod: RTC: Don't assume lock/unlock will be called with irq enabled ARM: OMAP2+: prm44xx: Introduce context save/restore for am43 PRCM IO Keerthy (1): OMAP: CLK: CLKSRC: Add suspend resume hooks Russ Dill (7): ARM: OMAP2: Add functions to save and restore clockdomain context en-masse. ARM: OMAP2: Add functions to save and restore omap hwmod context en-masse. ARM: OMAP2: Add functions to save and restore powerdomain context ARM: AM33XX: Add functions to save/restore am33xx control registers. ARM: OMAP2: Add functions to save and restore pinctrl context. ARM: OMAP2: Drop the concept of certain power domains not being able to lose context. gpio: omap: Drop the concept of gpio banks not being able to lose context. Tero Kristo (1): ARM: AM43XX: Add functions to save/restore am43xx control registers arch/arm/mach-omap2/clockdomain.c | 46 +++++ arch/arm/mach-omap2/clockdomain.h | 8 + arch/arm/mach-omap2/cm33xx.c | 53 ++++++ arch/arm/mach-omap2/cminst44xx.c | 43 +++++ arch/arm/mach-omap2/control.c | 172 ++++++++++++++++++ arch/arm/mach-omap2/control.h | 65 +++++++ arch/arm/mach-omap2/omap_device.c | 50 +++++ arch/arm/mach-omap2/omap_device.h | 1 + arch/arm/mach-omap2/omap_hwmod.c | 202 +++++++++++++++++++++ arch/arm/mach-omap2/omap_hwmod.h | 21 +++ .../mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c | 14 +- arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 3 +- arch/arm/mach-omap2/omap_hwmod_reset.c | 12 +- arch/arm/mach-omap2/powerdomain.c | 75 +++++--- arch/arm/mach-omap2/powerdomain.h | 8 +- arch/arm/mach-omap2/prm.h | 2 + arch/arm/mach-omap2/prm33xx.c | 31 ++++ arch/arm/mach-omap2/prm44xx.c | 79 ++++++++ arch/arm/mach-omap2/timer.c | 37 ++++ drivers/gpio/gpio-omap.c | 40 ++-- drivers/memory/ti-emif-pm.c | 24 +++ drivers/pinctrl/core.c | 1 + drivers/pinctrl/core.h | 1 - drivers/pinctrl/pinctrl-single.c | 50 +++++ drivers/pinctrl/pinmux.c | 22 +++ include/linux/pinctrl/pinctrl.h | 7 + include/linux/pinctrl/pinmux.h | 16 ++ include/linux/platform_data/gpio-omap.h | 1 - 28 files changed, 1019 insertions(+), 65 deletions(-) -- 1.9.1