Received: by 10.192.165.156 with SMTP id m28csp2092723imm; Thu, 12 Apr 2018 08:29:44 -0700 (PDT) X-Google-Smtp-Source: AIpwx49weYSk12jJK9vyrbIfyKHJxz43P2iSFpm/vKgAaXf891y/1mOkZsLdxUTwMaGVPIiFnh6Q X-Received: by 10.101.93.7 with SMTP id e7mr1071115pgr.119.1523546984226; Thu, 12 Apr 2018 08:29:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1523546984; cv=none; d=google.com; s=arc-20160816; b=WBKD9EnAHOLad5BQoSdDWEZ5+mbbGc30ly2LHephhC4AMXDZ6vTG4suKFpnjAO1cEC WQi56nbwh2r6G4P7hI8WtUTAGKI0I88x+Zt/OmhrMdlEdZOHhsa7RDOl1T9y+2/zx0Dj jL8fg4Qv4FIxc/mYgUHqsm0CaDLMoXAJ+lJDPITBb2N7jATBlKMdLFR1AeAdhEtgbVRo k8Ndx6BPk9CjVxGn6DlCRz71RAOMVUgephU7B7+J31bZ7rZ1H8ekkBNSILiG1VM1aaXS gGT+lp5Z5S6QeZwaURJN+Pb4E8DkhClIJ1dpPuO3aflbe75gWhpCjbNTDizKBlem6E9c rhiA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:content-transfer-encoding :content-language:accept-language:in-reply-to:references:message-id :date:thread-index:thread-topic:subject:cc:to:from :arc-authentication-results; bh=IDNgazI4duwYxj3O7l5h5fPGVYBXNlKoyBWco9zpdwY=; b=JCgSJ9HN84Fb0t2NlIdzUO8/KKh/Zdso8NgLAtjsRDzCevFIEifFfiNzMAohl5ajH4 pf6sd45kYI3bsAraQwGhp+XxlqwafmovWPdJgdXNYN75WY5/fFLYdMjBfEeDVuu3lIT/ X3+WBPiq8LWP+zRbAYDSyf90eHNjxUb/b9JxpGZNs0xRFqgKoDRtLBwOlONaJTrlrKSP f2vbdPT6urFlItU3sFidEB9bXyHDuuIS7Pi+ZxPo55ZZSe8sY3/gGr7s765FLCBYCn7b U7rk+uQsKQSL3jJDNmV9Sdhp2dT8YptW5ffll7ukWMgZLK/cIbdppUPoXJLt+5Dx0gIA 8v4g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t25si2640518pfh.101.2018.04.12.08.29.06; Thu, 12 Apr 2018 08:29:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754134AbeDLPVN convert rfc822-to-8bit (ORCPT + 99 others); Thu, 12 Apr 2018 11:21:13 -0400 Received: from esa2.microchip.iphmx.com ([68.232.149.84]:24743 "EHLO esa2.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753625AbeDLPVL (ORCPT ); Thu, 12 Apr 2018 11:21:11 -0400 X-IronPort-AV: E=Sophos;i="5.48,442,1517900400"; d="scan'208";a="13105923" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/DHE-RSA-AES256-SHA; 12 Apr 2018 08:21:10 -0700 Received: from CHN-SV-EXMX02.mchp-main.com ([fe80::7dfe:3761:863e:3963]) by CHN-SV-EXCH04.mchp-main.com ([::1]) with mapi id 14.03.0352.000; Thu, 12 Apr 2018 08:21:09 -0700 From: To: , CC: , , , , , , , , , , , , Subject: RE: [PATCH 3/4] lan78xx: Read LED modes from Device Tree Thread-Topic: [PATCH 3/4] lan78xx: Read LED modes from Device Tree Thread-Index: AQHT0mYDUWzYJ1048kSod0NWy6oe+6P9p/WA//+U1pA= Date: Thu, 12 Apr 2018 15:21:09 +0000 Message-ID: <9235D6609DB808459E95D78E17F2E43D40D17852@CHN-SV-EXMX02.mchp-main.com> References: <1523541336-145953-1-git-send-email-phil@raspberrypi.org> <1523541336-145953-4-git-send-email-phil@raspberrypi.org> <20180412143655.GQ28963@lunn.ch> In-Reply-To: <20180412143655.GQ28963@lunn.ch> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.10.76.4] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > > @@ -2097,6 +2098,25 @@ static int lan78xx_phy_init(struct lan78xx_net *dev) > > (void)lan78xx_set_eee(dev->net, &edata); > > } > > > > + if (!of_property_read_u32_array(dev->udev->dev.of_node, > > + "microchip,led-modes", > > + led_modes, ARRAY_SIZE(led_modes))) { > > + u32 reg; > > + int i; > > + > > + reg = phy_read(phydev, 0x1d); > > + for (i = 0; i < ARRAY_SIZE(led_modes); i++) { > > + reg &= ~(0xf << (i * 4)); > > + reg |= (led_modes[i] & 0xf) << (i * 4); > > + } > > + (void)phy_write(phydev, 0x1d, reg); > > Poking PHY registers directly from the MAC driver is not always a good > idea. This MAC driver does that in a few places :-( Agree but, some are for workaround unfortunately. > What do we know about the PHY? It is built into the device or is it > external? If it is external, how do you know the LED register is at > 0x1d? This register is not defined in include/linux/microchipphy.h. :( Also agree that there parts should be applied to internal PHY only.