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[74.125.82.169]) by smtp.gmail.com with ESMTPSA id m65-v6sm3639643oik.11.2018.04.12.15.07.45 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 12 Apr 2018 15:07:46 -0700 (PDT) Received: by mail-ot0-f169.google.com with SMTP id j8-v6so7771289ota.7 for ; Thu, 12 Apr 2018 15:07:45 -0700 (PDT) X-Received: by 2002:a9d:4376:: with SMTP id y51-v6mr2005160oti.329.1523570865451; Thu, 12 Apr 2018 15:07:45 -0700 (PDT) MIME-Version: 1.0 References: <1523390893-10904-1-git-send-email-rishabhb@codeaurora.org> <1523390893-10904-2-git-send-email-rishabhb@codeaurora.org> In-Reply-To: <1523390893-10904-2-git-send-email-rishabhb@codeaurora.org> From: Evan Green Date: Thu, 12 Apr 2018 22:07:10 +0000 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v4 1/2] Documentation: Documentation for qcom, llcc To: rishabhb@codeaurora.org Cc: linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm@lists.infradead.org, linux-kernel@vger.kernel.org, tsoni@codeaurora.org, kyan@codeaurora.org, ckadabi@codeaurora.org, stanimir.varbanov@linaro.org Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Apr 10, 2018 at 1:09 PM Rishabh Bhatnagar wrote: > Documentation for last level cache controller device tree bindings, > client bindings usage examples. > Signed-off-by: Channagoud Kadabi > Signed-off-by: Rishabh Bhatnagar > --- > .../devicetree/bindings/arm/msm/qcom,llcc.txt | 58 ++++++++++++++++++++++ > 1 file changed, 58 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt > diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt > new file mode 100644 > index 0000000..497cf0f > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt > @@ -0,0 +1,58 @@ > +== Introduction== > + > +LLCC (Last Level Cache Controller) provides last level of cache memory in SOC, > +that can be shared by multiple clients. Clients here are different cores in the > +SOC, the idea is to minimize the local caches at the clients and migrate to > +common pool of memory > + > +Properties: > +- compatible: > + Usage: required > + Value type: > + Definition: must be "qcom,sdm845-llcc" > + > +- reg: > + Usage: required > + Value Type: > + Definition: must be addresses and sizes of the LLCC registers > + > +- #cache-cells: > + Usage: required > + Value Type: > + Definition: Number of cache cells, must be 1 > + > +- max-slices: > + usage: required > + Value Type: > + Definition: Number of cache slices supported by hardware > + > +Example: > + > + llcc: qcom,llcc@1100000 { > + compatible = "qcom,sdm845-llcc"; > + reg = <0x1100000 0x250000>; > + #cache-cells = <1>; > + max-slices = <32>; > + }; > + > +== Client == > + > +Properties: > +- cache-slice-names: > + Usage: required > + Value type: > + Definition: A set of names that identify the usecase names of a > + client that uses cache slice. These strings are > + used to look up the cache slice entries by name. > + > +- cache-slices: > + Usage: required > + Value type: > + Definition: The tuple has phandle to llcc device as the first > + argument and the second argument is the usecase > + id of the client. > +For Example: > + venus { > + cache-slice-names = "vidsc0", "vidsc1"; > + cache-slices = <&llcc VIDSC0_ID>, <&llcc VIDSC1_ID>; My git complains about some whitespace weirdness on the line above. Other than that: Reviewed-by: Evan Green -Evan