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[209.132.180.67]) by mx.google.com with ESMTP id z30si4657995pfg.140.2018.04.13.05.47.56; Fri, 13 Apr 2018 05:48:10 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=VY9yB6Q/; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754676AbeDMMSa (ORCPT + 99 others); Fri, 13 Apr 2018 08:18:30 -0400 Received: from mail-qk0-f176.google.com ([209.85.220.176]:40141 "EHLO mail-qk0-f176.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754494AbeDMMS2 (ORCPT ); Fri, 13 Apr 2018 08:18:28 -0400 Received: by mail-qk0-f176.google.com with SMTP id o64so8786985qkl.7; Fri, 13 Apr 2018 05:18:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=YX7MNL6g6M+/vMEiH6O2P48SebxLjocjVYMjbli06qw=; b=VY9yB6Q/aSxeIlAZ6eQlwv5Fv7TGYjFlJCjMmQt1osu/QW4hsa4r6kPruL39b5zx5f F4fcN3vzrR7HZ/spy+WxYUKoKgPxj3oA45/lvn4kC0m8HEOEYDgPRRc7ggU2+CK4jTAr hYAbB/U2TlmQVCVFcE3pSGnmQl5M1lLp/n5xJjpyZ1j7DFSzCb46XUnn+y9zsDt2YyYh J1aP+/lC47CePoPSMcpRF8nwp5VhPznA7UsJqEVuZsYfmZ1512cRUrXRl5F/AhwPsNrY SVbn9MTzRJej0/L2hViHwKOR/IscM4wttsBMJUNJlv5CBa/PEPN9v0KNI+sMn3ZLiqfU Z4LQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=YX7MNL6g6M+/vMEiH6O2P48SebxLjocjVYMjbli06qw=; b=pRjKzUeRR33NKe1QTneef91i1zdN6ztmxifgPF366j5j3ANSWLsg7MgwxUZ78EZAqr k6TZ4E+8DOZVJLOlyUIQJUOmoaDHAMfqVPwKb2I1IfQzyfdkUiTQfdWAWTO7M/QxA1ie G2H1T2JzJNG15iias2RSSVQfHPl0HUqbsJ8uw7JvaREybzcH2bjTtWX9enVr4Rf1w6G8 6q1xNyI69oJuGR5K1HYWkm2BZPKFgmWiNhb44zDxAcWiMqcVyoUFIFngG7KqVeddRxFH kN6FRLgGA6geOK4tmnlWC//6/Ih6/WRbPyfU4yQgbHU9erPgfpr9FNRHNl01cO+VfSWY SZYw== X-Gm-Message-State: ALQs6tBDMYw+ujPpKFRTSDzAlD2yKF2zN68n03fsIL5pXiUoZwET9MvN WUVNEoc9GLZq9jYmD6w64Bb2XKacBbm+Q6WGRbY= X-Received: by 10.55.40.19 with SMTP id o19mr799243qkh.129.1523621907231; Fri, 13 Apr 2018 05:18:27 -0700 (PDT) MIME-Version: 1.0 Received: by 10.55.200.134 with HTTP; Fri, 13 Apr 2018 05:18:26 -0700 (PDT) In-Reply-To: <20180413120958.vo4y34q36q2rjyej@flea> References: <20180411124325.youvfpws27l2wesf@flea> <20180413120958.vo4y34q36q2rjyej@flea> From: Jagan Teki Date: Fri, 13 Apr 2018 17:48:26 +0530 Message-ID: Subject: Re: [PATCH v4 0/8] drm/sun4i: Allwinner MIPI-DSI support To: Maxime Ripard Cc: Thierry Reding , Chen-Yu Tsai , Mark Rutland , Rob Herring , Frank Rowand , dri-devel@lists.freedesktop.org, Gustavo Padovan , Daniel Vetter , Maarten Lankhorst , Sean Paul , devicetree , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Thomas Petazzoni Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Apr 13, 2018 at 5:39 PM, Maxime Ripard wrote: > On Fri, Apr 13, 2018 at 05:30:04PM +0530, Jagan Teki wrote: >> On Wed, Apr 11, 2018 at 6:13 PM, Maxime Ripard >> wrote: >> > On Wed, Apr 04, 2018 at 11:57:08AM +0200, Maxime Ripard wrote: >> >> Hi, >> >> >> >> Here is an preliminary version of the MIPI-DSI support for the Allwinner >> >> SoCs. >> >> >> >> This controller can be found on a number of recent SoCs, such as the >> >> A31, A33 or the A64. >> >> >> >> Given the sparse documentation, there's a number of obscure areas, but >> >> the current implementation has been tested with a 4-lanes DSI panel on >> >> an A33. >> >> >> >> The support is a bit rough around the edges at the time, and some artifacts >> >> are still shown on the screen for some reasons. Wider testing with >> >> different display will hopefully nail those down. >> >> >> >> This needs the regmap_mmio_attach_clk, on its way to Linus in 4.17. >> >> >> >> Let me know what you think, >> >> Maxime >> >> >> >> Changes from v3: >> >> - Rebased on top of current drm-misc-next >> >> - Switched to SPDX license header >> >> - Made the ECC array const >> >> - Split the big DSI patch into two, one to add the DSI driver and one to >> >> add the TCON bits. >> >> - Removed the dithering code >> >> - Changed the DT labels to remove the indices >> >> - Used sleeps instead of delays in the panel driver >> >> - Used the backlight_enable / _disable functions >> >> - Added Chen-Yu's Reviewed-by >> >> >> >> Changes from v2: >> >> - Added a ports node under the DSI node >> >> - Changed the huarui panel driver to an ili9881c driver >> >> - Changed the panel vendor to bananapi >> >> - Made the init table static in the panel driver >> >> - Dropped the huarui vendor patch for the DT doc. >> >> >> >> Changes from v1: >> >> - Rebased on 4.16-rc1 >> >> - Constified a few function arguments and structures >> >> - Reworked the DT binding example a bit >> >> - Reworked the panel driver to check for DSI return codes, and use DCS >> >> helpers when possible >> >> >> >> Maxime Ripard (8): >> >> drm/sun4i: tcon: Add TRI finish interrupt for vblank >> >> dt-bindings: display: Add Allwinner MIPI-DSI bindings >> >> drm/sun4i: Add Allwinner A31 MIPI-DSI controller support >> >> drm/sun4i: Tie the DSI controller in the TCON >> >> dt-bindings: panel: Add the Ilitek ILI9881c panel documentation >> >> drm/panel: Add Ilitek ILI9881c panel driver >> >> ARM: dts: sun8i: a33: Add the DSI-related nodes >> >> [DO NOT MERGE] arm: dts: sun8i: bpi-m2m: Add DSI display >> >> I have reviewed most of the patches and reused for A64 all look fine >> to me (except the panel driver). May be my issue is not relevant to >> this thread, but I'm looking for help If I miss anything for A64 [1] >> and [2] are changes made for A64, the issue is kernel hang while >> loading sun6i_dsi. > > My guess would be that you're not claiming the DE2 SRAM. See: > https://lkml.org/lkml/2018/3/16/1096 Thanks Maxime, will try.