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[209.132.180.67]) by mx.google.com with ESMTP id f2si5431093pgr.67.2018.04.13.19.38.18; Fri, 13 Apr 2018 19:39:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=SrOsuFDZ; dkim=pass header.i=@codeaurora.org header.s=default header.b=kyAII1Xn; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751940AbeDNChD (ORCPT + 99 others); Fri, 13 Apr 2018 22:37:03 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:54998 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751793AbeDNChA (ORCPT ); Fri, 13 Apr 2018 22:37:00 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 3F7FA60767; Sat, 14 Apr 2018 02:37:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1523673420; bh=aHm7tuHmYyaTr9lAMoiiC5vXjNAatgkEwd7bTduH8TE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SrOsuFDZINULeM7ROa3cju2qOSQifBDHFpSm0LiQjq+4qjrTW5bAMkS45P3aj2cGt I4e8lPpDaWZ8OJBFpX3TqiqPeUel0P46zpus0mlBpNMeMKNA6HbvSahRTLq6aKERg9 o3tYVeNaWQnGmrj+wYV8ZCHow8o4kdsbMUUszCjk= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from tdas-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: tdas@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 0EFD960BFA; Sat, 14 Apr 2018 02:36:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1523673419; bh=aHm7tuHmYyaTr9lAMoiiC5vXjNAatgkEwd7bTduH8TE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kyAII1XnFA3L9TZ/B9kOxcvXOYSnT3KLK1/FMLrjTxibOkKIVhD7l/8v8FkJfWs3h oC0M38jpmycmA2K0CUtycq0OBp1tPXvebwwxQ3VgXb9yW02Lp+MRdHPojoRc3JE0Vl rMgnOCuZJDUelxPZRxXKPMKBcI7cDtyrqiNZrmXA= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 0EFD960BFA Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=tdas@codeaurora.org From: Taniya Das To: Stephen Boyd , Michael Turquette Cc: Andy Gross , David Brown , Rajendra Nayak , Odelu Kukatla , Amit Nischal , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Taniya Das Subject: [PATCH v3 1/2] dt-bindings: clock: Introduce QCOM RPMh clock bindings Date: Sat, 14 Apr 2018 08:06:40 +0530 Message-Id: <1523673401-21611-2-git-send-email-tdas@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1523673401-21611-1-git-send-email-tdas@codeaurora.org> References: <1523673401-21611-1-git-send-email-tdas@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add RPMh clock device bindings for Qualcomm Technology Inc's SoCs. These devices would be used for communicating resource state requests to control the clocks managed by RPMh. Signed-off-by: Amit Nischal Signed-off-by: Taniya Das --- .../devicetree/bindings/clock/qcom,rpmh-clk.txt | 22 ++++++++++++++++++++ include/dt-bindings/clock/qcom,rpmh.h | 24 ++++++++++++++++++++++ 2 files changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,rpmh-clk.txt create mode 100644 include/dt-bindings/clock/qcom,rpmh.h diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmh-clk.txt b/Documentation/devicetree/bindings/clock/qcom,rpmh-clk.txt new file mode 100644 index 0000000..3c00765 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,rpmh-clk.txt @@ -0,0 +1,22 @@ +Qualcomm Technologies, Inc. RPMh Clocks +------------------------------------------------------- + +Resource Power Manager Hardened (RPMh) manages shared resources on +some Qualcomm Technologies Inc. SoCs. It accepts clock requests from +other hardware subsystems via RSC to control clocks. + +Required properties : +- compatible : shall contain "qcom,sdm845-rpmh-clk" + +- #clock-cells : must contain 1 + +Example : + +#include + + &apps_rsc { + rpmhcc: clock-controller { + compatible = "qcom,sdm845-rpmh-clk"; + #clock-cells = <1>; + }; + }; diff --git a/include/dt-bindings/clock/qcom,rpmh.h b/include/dt-bindings/clock/qcom,rpmh.h new file mode 100644 index 0000000..36caab2 --- /dev/null +++ b/include/dt-bindings/clock/qcom,rpmh.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */ + + +#ifndef _DT_BINDINGS_CLK_MSM_RPMH_H +#define _DT_BINDINGS_CLK_MSM_RPMH_H + +/* RPMh controlled clocks */ +#define RPMH_CXO_CLK 0 +#define RPMH_CXO_CLK_A 1 +#define RPMH_LN_BB_CLK2 2 +#define RPMH_LN_BB_CLK2_A 3 +#define RPMH_LN_BB_CLK3 4 +#define RPMH_LN_BB_CLK3_A 5 +#define RPMH_RF_CLK1 6 +#define RPMH_RF_CLK1_A 7 +#define RPMH_RF_CLK2 8 +#define RPMH_RF_CLK2_A 9 +#define RPMH_RF_CLK3 10 +#define RPMH_RF_CLK3_A 11 +#define RPMH_RF_CLK4 12 +#define RPMH_RF_CLK4_A 13 + +#endif -- Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.