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[209.132.180.67]) by mx.google.com with ESMTP id c1-v6si12115955pll.449.2018.04.16.01.44.08; Mon, 16 Apr 2018 01:44:22 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=synopsys.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754101AbeDPImR (ORCPT + 99 others); Mon, 16 Apr 2018 04:42:17 -0400 Received: from us01smtprelay-2.synopsys.com ([198.182.47.9]:59980 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752941AbeDPImQ (ORCPT ); Mon, 16 Apr 2018 04:42:16 -0400 Received: from mailhost.synopsys.com (mailhost2.synopsys.com [10.13.184.66]) by smtprelay.synopsys.com (Postfix) with ESMTP id 9901B24E0D27; Mon, 16 Apr 2018 01:42:15 -0700 (PDT) Received: from pt02.synopsys.com (pt02.internal.synopsys.com [10.107.23.240]) by mailhost.synopsys.com (Postfix) with ESMTP id 110F131A0; Mon, 16 Apr 2018 01:42:15 -0700 (PDT) Received: from [127.0.0.1] (gustavo-e7480.internal.synopsys.com [10.107.25.102]) by pt02.synopsys.com (Postfix) with ESMTP id 64F753E048; Mon, 16 Apr 2018 09:42:14 +0100 (WEST) Subject: Re: [PATCH v2 8/9] PCI: dwc: Small computation improvement To: Jingoo Han , "bhelgaas@google.com" , "lorenzo.pieralisi@arm.com" , "Joao.Pinto@synopsys.com" , "kishon@ti.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" Cc: "linux-pci@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" References: <5181f7ffbb9d2889974c49d84e72042251adf8b6.1523266508.git.gustavo.pimentel@synopsys.com> <003001d3d128$39f3eaa0$addbbfe0$@gmail.com> <000001d3d1cc$92706790$b75136b0$@gmail.com> From: Gustavo Pimentel Message-ID: <6a947227-12f5-bc67-71bc-d6d67eb9e98f@synopsys.com> Date: Mon, 16 Apr 2018 09:41:11 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: <000001d3d1cc$92706790$b75136b0$@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Jingoo, On 11/04/2018 20:37, Jingoo Han wrote: > On Wednesday, April 11, 2018 3:40 AM, Gustavo Pimentel wrote: >> >> Hi Jingoo, >> >> On 11/04/2018 01:01, Jingoo Han wrote: >>> On Monday, April 9, 2018 5:41 AM, Gustavo Pimentel wrote: >>>> >>>> Replaces a simple division by 2 to a right shift rotation of 1 bit. >>> >>> It looks good. However, would you add a simple reason to the commit >>> message? >> >> Sure. >> >> Can be this one? >> >> Probably any recent and decent compiler does this kind of substitution >> in order to improve code performance. Nevertheless it's a coding good >> practice whenever there is a division / multiplication by multiple of 2 >> to replace it by the equivalent operation in this case, the shift >> rotation. > > Yes, that's what I wanted. The most platforms using 'dwc' are based on > ARM CPUs. So, the shift rotation can be better. > Thank you. Can I get your acked-by on this? > > Best regards, > Jingoo Han > >> >>> >>> Best regards, >>> Jingoo Han >>> >>>> >>>> Signed-off-by: Gustavo Pimentel >>>> --- >>>> Change v1->v2: >>>> - Nothing changed, just to follow the patch set version. >>>> >>>> drivers/pci/dwc/pcie-designware-host.c | 8 ++++---- >>>> 1 file changed, 4 insertions(+), 4 deletions(-) >>>> >>>> diff --git a/drivers/pci/dwc/pcie-designware-host.c >>>> b/drivers/pci/dwc/pcie-designware-host.c >>>> index 03e9b82..8e6fed4 100644 >>>> --- a/drivers/pci/dwc/pcie-designware-host.c >>>> +++ b/drivers/pci/dwc/pcie-designware-host.c >>>> @@ -332,8 +332,8 @@ int dw_pcie_host_init(struct pcie_port *pp) >>>> >>>> cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, >>>> "config"); >>>> if (cfg_res) { >>>> - pp->cfg0_size = resource_size(cfg_res) / 2; >>>> - pp->cfg1_size = resource_size(cfg_res) / 2; >>>> + pp->cfg0_size = resource_size(cfg_res) >> 1; >>>> + pp->cfg1_size = resource_size(cfg_res) >> 1; >>>> pp->cfg0_base = cfg_res->start; >>>> pp->cfg1_base = cfg_res->start + pp->cfg0_size; >>>> } else if (!pp->va_cfg0_base) { >>>> @@ -377,8 +377,8 @@ int dw_pcie_host_init(struct pcie_port *pp) >>>> break; >>>> case 0: >>>> pp->cfg = win->res; >>>> - pp->cfg0_size = resource_size(pp->cfg) / 2; >>>> - pp->cfg1_size = resource_size(pp->cfg) / 2; >>>> + pp->cfg0_size = resource_size(pp->cfg) >> 1; >>>> + pp->cfg1_size = resource_size(pp->cfg) >> 1; >>>> pp->cfg0_base = pp->cfg->start; >>>> pp->cfg1_base = pp->cfg->start + pp->cfg0_size; >>>> break; >>>> -- >>>> 2.7.4 >>>> >>> >>> >> >> Regards, >> Gustavo > > Regards, Gustavo