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[209.132.180.67]) by mx.google.com with ESMTP id k33-v6si11844874pld.158.2018.04.16.04.45.28; Mon, 16 Apr 2018 04:45:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753707AbeDPJ1F (ORCPT + 99 others); Mon, 16 Apr 2018 05:27:05 -0400 Received: from zxshcas1.zhaoxin.com ([180.169.121.91]:35747 "EHLO ZXSHCAS1.zhaoxin.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1752999AbeDPJ1E (ORCPT ); Mon, 16 Apr 2018 05:27:04 -0400 Received: from zxbjmbx3.zhaoxin.com (10.29.252.165) by ZXSHCAS1.zhaoxin.com (10.28.252.161) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1261.35; Mon, 16 Apr 2018 17:27:01 +0800 Received: from timguo-System-Product-Name.zhaoxin.com (10.29.8.54) by zxbjmbx3.zhaoxin.com (10.29.252.165) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1261.35; Mon, 16 Apr 2018 17:27:00 +0800 From: David Wang To: , , , , , CC: , , , , , , David Wang Subject: [PATCH] x86/dma-mapping: override via_no_dac for new VIA PCI bridges Date: Mon, 16 Apr 2018 17:26:56 +0800 Message-ID: <1523870816-6214-1-git-send-email-davidwang@zhaoxin.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.29.8.54] X-ClientProxiedBy: zxbjmbx1.zhaoxin.com (10.29.252.163) To zxbjmbx3.zhaoxin.com (10.29.252.165) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org PCI bridges integrated in new VIA chipset/SoC have no DAC issue. Enable DAC for the platforms with these chipset/SoC can improve DMA performance about 20% when DRAM size > 4GB. Signed-off-by: David Wang --- arch/x86/kernel/pci-dma.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/x86/kernel/pci-dma.c b/arch/x86/kernel/pci-dma.c index cb9c1fa..6e37b0e 100644 --- a/arch/x86/kernel/pci-dma.c +++ b/arch/x86/kernel/pci-dma.c @@ -47,6 +47,10 @@ extern struct iommu_table_entry __iommu_table[], __iommu_table_end[]; +#ifdef CONFIG_PCI +static int override_via_dac __read_mostly; +#endif + /* Dummy device used for NULL arguments (normally ISA). */ struct device x86_dma_fallback_dev = { .init_name = "fallback device", @@ -279,6 +283,9 @@ static int __init pci_iommu_init(void) static void via_no_dac(struct pci_dev *dev) { + if (override_via_dac) + return; + if (forbid_dac == 0) { dev_info(&dev->dev, "disabling DAC on VIA PCI bridge\n"); forbid_dac = 1; @@ -286,4 +293,19 @@ static void via_no_dac(struct pci_dev *dev) } DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI, 8, via_no_dac); + +static void via_can_dac(struct pci_dev *dev) +{ + /* + * New VIA bridges have no issues for DAC. + * Disable the "via_no_dac" fixup code for these new VIA bridges. + */ + override_via_dac = 1; +} +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, 0x345B, + PCI_CLASS_BRIDGE_ISA, 8, via_can_dac); +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, 0x1001, + PCI_CLASS_BRIDGE_ISA, 8, via_can_dac); +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, 0x300A, + PCI_CLASS_BRIDGE_ISA, 8, via_can_dac); #endif -- 1.9.1