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Violators will be prosecuted; Tue, 17 Apr 2018 05:09:44 +0100 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w3H49h3C6029752; Tue, 17 Apr 2018 04:09:43 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 11D68AE053; Tue, 17 Apr 2018 04:59:34 +0100 (BST) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9FA7EAE045; Tue, 17 Apr 2018 04:59:33 +0100 (BST) Received: from ozlabs.au.ibm.com (unknown [9.192.253.14]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 17 Apr 2018 04:59:33 +0100 (BST) Received: from [10.61.2.125] (haven.au.ibm.com [9.192.254.114]) (using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) by ozlabs.au.ibm.com (Postfix) with ESMTPSA id 65A8EA0195; Tue, 17 Apr 2018 14:09:41 +1000 (AEST) Subject: Re: [PATCH 1/7] powerpc: Add TIDR CPU feature for Power9 To: "Alastair D'Silva" , linuxppc-dev@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, mikey@neuling.org, vaibhav@linux.vnet.ibm.com, aneesh.kumar@linux.vnet.ibm.com, malat@debian.org, felix@linux.vnet.ibm.com, pombredanne@nexb.com, sukadev@linux.vnet.ibm.com, npiggin@gmail.com, gregkh@linuxfoundation.org, arnd@arndb.de, fbarrat@linux.vnet.ibm.com, corbet@lwn.net, "Alastair D'Silva" References: <20180417020950.21446-1-alastair@au1.ibm.com> <20180417020950.21446-2-alastair@au1.ibm.com> From: Andrew Donnellan Date: Tue, 17 Apr 2018 14:09:41 +1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: <20180417020950.21446-2-alastair@au1.ibm.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-AU Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 x-cbid: 18041704-0008-0000-0000-000004EC150D X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18041704-0009-0000-0000-00001E80165A Message-Id: <68ec9aff-b523-dd30-cd73-42dc8c792ba1@au1.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2018-04-17_02:,, signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1804170038 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 17/04/18 12:09, Alastair D'Silva wrote: > diff --git a/arch/powerpc/include/asm/switch_to.h b/arch/powerpc/include/asm/switch_to.h > index be8c9fa23983..5b03d8a82409 100644 > --- a/arch/powerpc/include/asm/switch_to.h > +++ b/arch/powerpc/include/asm/switch_to.h > @@ -94,6 +94,5 @@ static inline void clear_task_ebb(struct task_struct *t) > extern int set_thread_uses_vas(void); > > extern int set_thread_tidr(struct task_struct *t); > -extern void clear_thread_tidr(struct task_struct *t); This hunk looks like it really belongs in patch 3. Apart from that, I'm not really familiar with the CPU features code but nothing seems overly wrong... Reviewed-by: Andrew Donnellan -- Andrew Donnellan OzLabs, ADL Canberra andrew.donnellan@au1.ibm.com IBM Australia Limited