Received: by 10.192.165.156 with SMTP id m28csp1413916imm; Mon, 16 Apr 2018 21:39:30 -0700 (PDT) X-Google-Smtp-Source: AIpwx48+5rreOId9y0jSep8UpaelOB7DVsEx1vHBbkBXzoyLEc4SgnVmrygnp3wOWm11TER6ufac X-Received: by 10.101.82.197 with SMTP id z5mr528157pgp.45.1523939970157; Mon, 16 Apr 2018 21:39:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1523939970; cv=none; d=google.com; s=arc-20160816; b=v4+fuEPe/7Rxu4Hg4HweOM7hiVXRnCR/NWYwrAi2uCDlIP6v0+UrZ2ZhxDG7QtXTA3 IiObUAn18OP0fVMmDuRn2n7AhE8stn0e7599JNZcdacAfzUQXrrd0HlIRZQfe1mqXQE5 HpQhf1Q8HkLBTH97zhOCp/Sc6vAA8qcSKdQFqAkZgPIiDl797s62esUZdktis23IuTKJ FS6kzSLbBc9sZhWnlCs75M0+GLsRMhfarmSwx5gdVi50/Go+mPa8ouz24H10D+r+Lalc J06//kEKMDzb3blj1fhXFFM9SO03Xg9fxg2GA3lNFgj6CO1sCh3NyX0zBBC2uUCvFMCF q9NA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:date:subject:user-agent:message-id :references:cc:in-reply-to:from:to:content-transfer-encoding :mime-version:dmarc-filter:arc-authentication-results; bh=+jeNhpJ2eh+TETMSdjSs35vxJLD3ZMlHLRQuWSSzm2Q=; b=jmTy2azn69Li5fWJLS6ZmpFdUQWldCcHCKSyKuc3MfyoqAf2v2pQB83gRiofZaEH6j Q1QQijgAL03p5X6aYxuJiGiE4juOTAzY73F/bkmD9hhtF4uy/DQf3YXAcREJ962y5yUP 7LTbH0peQX7h/n6D0zwidizTS1adqvodJkFvIBvMVOenDegob6R/6Fd6jf5PVmwnpZan 1cXsFfYqJzsJMl8lHJ6pag5C4kCVzyD963gZQcWY9rK69/O1P/mHFHT7EI6botQ64Tcn oKeVItfFfb9a601Y9nDMbLpZN+VCeEC5X67TXnERux/4KMf5xMnPVBoAsfKfBDBNJfpS UWBg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y5si11758055pfe.184.2018.04.16.21.39.15; Mon, 16 Apr 2018 21:39:30 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752259AbeDQEgH convert rfc822-to-8bit (ORCPT + 99 others); Tue, 17 Apr 2018 00:36:07 -0400 Received: from mail.kernel.org ([198.145.29.99]:59166 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751210AbeDQEgF (ORCPT ); Tue, 17 Apr 2018 00:36:05 -0400 Received: from localhost (unknown [104.132.1.75]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 2702821838; Tue, 17 Apr 2018 04:36:05 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2702821838 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=sboyd@kernel.org Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8BIT To: Amit Nischal , Michael Turquette , Stephen Boyd From: Stephen Boyd In-Reply-To: <1523254493-5313-2-git-send-email-anischal@codeaurora.org> Cc: Andy Gross , David Brown , Rajendra Nayak , Odelu Kukatla , Taniya Das , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Amit Nischal References: <1523254493-5313-1-git-send-email-anischal@codeaurora.org> <1523254493-5313-2-git-send-email-anischal@codeaurora.org> Message-ID: <152393976444.51482.14239555065542681076@swboyd.mtv.corp.google.com> User-Agent: alot/0.7 Subject: Re: [PATCH v4 1/3] clk: qcom: Clear hardware clock control bit of RCG Date: Mon, 16 Apr 2018 21:36:04 -0700 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Quoting Amit Nischal (2018-04-08 23:14:51) > For upcoming targets like sdm845, POR value of the hardware clock control > bit is set for most of root clocks which needs to be cleared for software > to be able to control. For older targets like MSM8996, this bit is reserved > bit and having POR value as 0 so this patch will work for the older targets > too. So update the configuration mask to take care of the same to clear > hardware clock control bit. > > Signed-off-by: Amit Nischal This one's already been applied. Please stop sending it.