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[209.132.180.67]) by mx.google.com with ESMTP id b3-v6si13942569plc.329.2018.04.17.03.32.34; Tue, 17 Apr 2018 03:32:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@bgdev-pl.20150623.gappssmtp.com header.s=20150623 header.b=IUbMXgSW; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752795AbeDQK36 (ORCPT + 99 others); Tue, 17 Apr 2018 06:29:58 -0400 Received: from mail-wr0-f195.google.com ([209.85.128.195]:41198 "EHLO mail-wr0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752709AbeDQK33 (ORCPT ); Tue, 17 Apr 2018 06:29:29 -0400 Received: by mail-wr0-f195.google.com with SMTP id v24so16957342wra.8 for ; Tue, 17 Apr 2018 03:29:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bgdev-pl.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/nCbi8kfWY4J9c9G0x+sjE4QOW4sey/0dqBXD6QxW0M=; b=IUbMXgSW6o7vVW6Pif1ZenQkRKVh3Gdg31ngnmFViZvePemVMjotrGUIMn1uV8WcOF ZF3PTQn5DfEc4i7mURjDid6Vj2Gebw6DFyhX2bra4fwBRbJAAJ3Tc5wQMMX5garVrzOo 2ynPRn/b2rHE5ui7ZzNBRMj5Sxx9NXrrQtn8tLE776T3RZy4x9LIsY3JTXwZZKcoL+CW dqDlbj0DO80ZWIFmZQImE01YeMGqkM96Zt8RyqVgZPAoRqvA0Djv5VLODyzrenQVnXxU arOE1HU1X01YS42Bcq48ubFycqdyv+DB/RCxitQf4FEuR+ze28LGa0FIkM5VH7yjvlZf hI6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/nCbi8kfWY4J9c9G0x+sjE4QOW4sey/0dqBXD6QxW0M=; b=JGwRbXA/CLW/OoYV3ACQE0Hkc///UKkPCwZjo4Op3Mn73uHAne2VqlgISy+Ku214k+ HSP2mwpf+sWiBRZzyrDWwIT70cBV3FOfTsUWmUaJ2BJJX6+cMyZJdO9oJGuUEMqHVLQn MlpMCL36oFs870GvzbajIGI5iKd/4cdP2HTLYN9qd3y5Uwse618FfUhf74pn6e6S9/hy sNkYMCpEp3B7nHfhMMVIXVT6DjU4LFYOpRp1K+f1UALfkUblfDIyzS95p1B/EcNxoNiL 5YF7U/tz6nc5NQN/iQop1ENuTALNXRIE9/eE8Zdb69eCb+OndXzNnF76caOMiXjNpQ1h qmxw== X-Gm-Message-State: ALQs6tCYH+DUI2h5j/GH9G9ma4XzCr/Uv6Rz890W/iA2mh65MbpNfcTr QykOCZn/QIcOgj8zDiJkBN981g== X-Received: by 10.223.175.40 with SMTP id z37mr1230236wrc.72.1523960968313; Tue, 17 Apr 2018 03:29:28 -0700 (PDT) Received: from brgl-bgdev.home ([2a01:cb1d:af:5b00:e837:b8d5:48c1:571b]) by smtp.gmail.com with ESMTPSA id r75sm8842252wmf.34.2018.04.17.03.29.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 17 Apr 2018 03:29:27 -0700 (PDT) From: Bartosz Golaszewski To: Sekhar Nori , Kevin Hilman , Russell King , Santosh Shilimkar Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Bartosz Golaszewski Subject: [RESEND PATCH v2 3/4] ARM: davinci: add aemif & nand support to da850-lcdk in legacy mode Date: Tue, 17 Apr 2018 12:29:16 +0200 Message-Id: <20180417102917.7794-4-brgl@bgdev.pl> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180417102917.7794-1-brgl@bgdev.pl> References: <20180417102917.7794-1-brgl@bgdev.pl> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Bartosz Golaszewski We now have support for aemif & nand from board files. As an example add support for nand to da850-lcdk in legacy mode. Signed-off-by: Bartosz Golaszewski --- arch/arm/mach-davinci/board-omapl138-hawk.c | 132 ++++++++++++++++++++ 1 file changed, 132 insertions(+) diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c index 6c997c59a3cd..9c3de56b54e4 100644 --- a/arch/arm/mach-davinci/board-omapl138-hawk.c +++ b/arch/arm/mach-davinci/board-omapl138-hawk.c @@ -16,6 +16,11 @@ #include #include #include +#include +#include +#include +#include +#include #include #include @@ -162,6 +167,129 @@ static __init void omapl138_hawk_mmc_init(void) gpiod_remove_lookup_table(&mmc_gpios_table); } +static struct mtd_partition omapl138_hawk_nandflash_partition[] = { + { + .name = "u-boot env", + .offset = 0, + .size = SZ_128K, + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "u-boot", + .offset = MTDPART_OFS_APPEND, + .size = SZ_128K, + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "free space", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0, + }, +}; + +static struct davinci_aemif_timing omapl138_hawk_nandflash_timing = { + .wsetup = 24, + .wstrobe = 21, + .whold = 14, + .rsetup = 19, + .rstrobe = 50, + .rhold = 0, + .ta = 20, +}; + +static struct davinci_nand_pdata omapl138_hawk_nandflash_data = { + .parts = omapl138_hawk_nandflash_partition, + .nr_parts = ARRAY_SIZE(omapl138_hawk_nandflash_partition), + .ecc_mode = NAND_ECC_HW, + .ecc_bits = 4, + .bbt_options = NAND_BBT_USE_FLASH, + .options = NAND_BUSWIDTH_16, + .timing = &omapl138_hawk_nandflash_timing, + .mask_chipsel = 0, + .mask_ale = 0, + .mask_cle = 0, +}; + +static struct resource omapl138_hawk_nandflash_resource[] = { + { + .start = DA8XX_AEMIF_CS3_BASE, + .end = DA8XX_AEMIF_CS3_BASE + SZ_32M, + .flags = IORESOURCE_MEM, + }, + { + .start = DA8XX_AEMIF_CTL_BASE, + .end = DA8XX_AEMIF_CTL_BASE + SZ_32K, + .flags = IORESOURCE_MEM, + }, +}; + +static struct resource omapl138_hawk_aemif_resource[] = { + { + .start = DA8XX_AEMIF_CTL_BASE, + .end = DA8XX_AEMIF_CTL_BASE + SZ_32K, + .flags = IORESOURCE_MEM, + } +}; + +static struct aemif_abus_data omapl138_hawk_aemif_abus_data[] = { + { + .cs = 3, + } +}; + +static struct platform_device omapl138_hawk_aemif_devices[] = { + { + .name = "davinci_nand", + .id = 1, + .dev = { + .platform_data = &omapl138_hawk_nandflash_data, + }, + .resource = omapl138_hawk_nandflash_resource, + .num_resources = ARRAY_SIZE(omapl138_hawk_nandflash_resource), + .id = 0, + } +}; + +static struct aemif_platform_data omapl138_hawk_aemif_pdata = { + .cs_offset = 2, + .abus_data = omapl138_hawk_aemif_abus_data, + .num_abus_data = ARRAY_SIZE(omapl138_hawk_aemif_abus_data), + .sub_devices = omapl138_hawk_aemif_devices, + .num_sub_devices = ARRAY_SIZE(omapl138_hawk_aemif_devices), +}; + +static struct platform_device omapl138_hawk_aemif_device = { + .name = "ti-aemif", + .dev = { + .platform_data = &omapl138_hawk_aemif_pdata, + }, + .resource = omapl138_hawk_aemif_resource, + .num_resources = ARRAY_SIZE(omapl138_hawk_aemif_resource), + .id = -1, +}; + +static const short omapl138_hawk_nand_pins[] = { + DA850_EMA_WAIT_1, DA850_NEMA_OE, DA850_NEMA_WE, DA850_NEMA_CS_3, + DA850_EMA_D_0, DA850_EMA_D_1, DA850_EMA_D_2, DA850_EMA_D_3, + DA850_EMA_D_4, DA850_EMA_D_5, DA850_EMA_D_6, DA850_EMA_D_7, + DA850_EMA_D_8, DA850_EMA_D_9, DA850_EMA_D_10, DA850_EMA_D_11, + DA850_EMA_D_12, DA850_EMA_D_13, DA850_EMA_D_14, DA850_EMA_D_15, + DA850_EMA_A_1, DA850_EMA_A_2, + -1 +}; + +static int omapl138_hawk_register_aemif(void) +{ + int ret; + + ret = davinci_cfg_reg_list(omapl138_hawk_nand_pins); + if (ret) + pr_warn("%s: NAND mux setup failed: %d\n", __func__, ret); + + return platform_device_register(&omapl138_hawk_aemif_device); +} + static irqreturn_t omapl138_hawk_usb_ocic_irq(int irq, void *dev_id); static da8xx_ocic_handler_t hawk_usb_ocic_handler; @@ -294,6 +422,10 @@ static __init void omapl138_hawk_init(void) omapl138_hawk_usb_init(); + ret = omapl138_hawk_register_aemif(); + if (ret) + pr_warn("%s: aemif registration failed: %d\n", __func__, ret); + ret = da8xx_register_watchdog(); if (ret) pr_warn("%s: watchdog registration failed: %d\n", -- 2.17.0