Received: by 10.192.178.70 with SMTP id s6csp1905735imc; Tue, 17 Apr 2018 05:37:02 -0700 (PDT) X-Google-Smtp-Source: AIpwx4+j1FdJhGPdvZvt5EvK0vlBC+kG6KsL2eAz3Zxe0X/zAZkHtuP1Re9koGevXhyoCBCEq8qM X-Received: by 10.98.130.140 with SMTP id w134mr1848046pfd.127.1523968622203; Tue, 17 Apr 2018 05:37:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1523968622; cv=none; d=google.com; s=arc-20160816; b=gy4bi8lcE9ZCDmkDXEHmhh1/hxK9/0a4Lg68MCiL2WAYr8imVzkY8DZj2tDOu1XOhs IW1NdefRH5rETnZBl9EBJM3oFIPBehdUDDQE6bJjP48XMJ+C24i09ebI7QJcUgcf7eyV wAsQKuU16JeqvfQiC0pkZroOjLnqp5OvHFSk3pip8Vr6kMz915nb4cF9P8wtip7boc3o y9gGEaFgb1hcEsMlKgklvN86dq/wVCOh8xWnoGKGFbZHuF/MPInrER23x3t14iia66qG BBwbsxHS4nXo7ftJGcZEgygPmUMVDVxxZ4xNMkNBmOSEs85qJsh6byZIvtjJjMXJhVeP TDUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:content-transfer-encoding :references:in-reply-to:date:cc:to:from:subject:message-id :arc-authentication-results; bh=OHK+CIJuPKjs+1r6/X2QejLcJnioY6lvELZVAbAWHlA=; b=yk+7whFN0BvJOhzl/h4TwMKYcsM15TkwnY3trd5bmL3deLBp9PKz/n27qJtAAgYjMX 77pSt3KdfJSRjCuzv1rgkRg0ifh+T+cjeOQG0tB7QYoQnXlnC3Iq1jYnSdNC7hrh4q8b shJlBePGKiWc6baTZPwyz05ynmEv8QtPWlCbJB4tKBlUlM9nFl9U7wrIawBhPRRdK7du 2N2BMJQ4fXm5KWH6sUraEVkjz/YTnI/51g8uHaXeHSJPQGvplK87TEGbouLTKrXDq0Yb dbW3W+m2S+AsIWWGOeZhZUAIYqr9+RoNdCRDdMyTnKJW+rkU9O7ApV4vh54g6BKh3KEK YKYQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m15si2775903pgu.98.2018.04.17.05.36.47; Tue, 17 Apr 2018 05:37:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753280AbeDQMfO (ORCPT + 99 others); Tue, 17 Apr 2018 08:35:14 -0400 Received: from Mailgw01.mediatek.com ([1.203.163.78]:30463 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1752974AbeDQMfN (ORCPT ); Tue, 17 Apr 2018 08:35:13 -0400 X-UUID: e1e012b193514423ac6be488c594c450-20180417 Received: from mtkcas32.mediatek.inc [(172.27.4.250)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 1427989747; Tue, 17 Apr 2018 20:35:07 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by MTKMBS33DR.mediatek.inc (172.27.6.106) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Tue, 17 Apr 2018 20:35:05 +0800 Received: from [172.21.77.33] (172.21.77.33) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Tue, 17 Apr 2018 20:35:05 +0800 Message-ID: <1523968505.23886.2.camel@mtkswgap22> Subject: Re: [PATCH] clk: mediatek: correct the clocks for MT2701 HDMI PHY module From: Ryder Lee To: Stephen Boyd CC: Matthias Brugger , chunhui dai , , , , Date: Tue, 17 Apr 2018 20:35:05 +0800 In-Reply-To: <152389649546.51482.15378110712126175925@swboyd.mtv.corp.google.com> References: <152389649546.51482.15378110712126175925@swboyd.mtv.corp.google.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.2.3-0ubuntu6 Content-Transfer-Encoding: 7bit MIME-Version: 1.0 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 2018-04-16 at 09:34 -0700, Stephen Boyd wrote: > Quoting Ryder Lee (2018-04-15 19:31:58) > > The hdmitx_dig_cts clock signal is not a child of clk26m, > > and the actual output of the PLL block is derived from > > the tvdpll via a configurable PLL post-divider. > > > > It is used as the PLL reference input to the HDMI PHY module. > > > > Signed-off-by: Chunhui Dai > > Signed-off-by: Ryder Lee > > Any sort of Fixes: tag here? > Yes, I've already sent a new one. Thanks