Received: by 10.192.165.156 with SMTP id m28csp74888imm; Tue, 17 Apr 2018 06:48:43 -0700 (PDT) X-Google-Smtp-Source: AIpwx4/NLC6ywQhDkEmeLpSqh4G+GTeoWncTBL0pcutv9PQVbgPiEwjcnRO618D5v2ewb057b1wp X-Received: by 10.99.3.22 with SMTP id 22mr1804249pgd.277.1523972922990; Tue, 17 Apr 2018 06:48:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1523972922; cv=none; d=google.com; s=arc-20160816; b=Um1IiR4l0kyPSP8u6BbJMLoSq1pMq7Oe0pF/V9IBI1HoeFjCUKSChsMjCiR4yoyAjm NfTka3O6sMkMuBFbp3Xrgyk8H8bEUkNWQF1tja6ZS6iqanSqA1B/enHSNy6NzjP+2t3e vXyj1i24mIkd+V9neVPhRAF00RxdYME+S7oFELKVG6jE+lwL6vxlswMdQ/BuUPlcz1Tx t9qiCGubMpoT7kJDdlenbm8KHwEXW1sZjBRvhGToVWXm5RTzdGrfKRPP+964xaZ9QhEk HMvBBmmjDxAZ3gqh2zu4Ft/dUiURT9ha7cpfDsr/gpRnnfHUKe/uJq+F99q/YIg24ycq UG1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from:arc-authentication-results; bh=fQn8UrSsf0Wz5kNrTb8A3vdCHvLtA6TUKve98QHC960=; b=fzDPQ6X+L7za0R5bduP34HQQzLZsc+SmH2gNzxi9LHdeO5PpUuCLNcaErmsk/AoWWI Hf30j4rhgAi6ZvC4+F3DTkU7PF7LZWvjHpRixH8S1KpcI8wG7c1NzklWYBGnJcoTf6pB rWZRaW9ECpXoZgYxHf9glzfRLGmrNs0xvSY+rd8D94X3O1LY3u5b7KO7QfrtZmUWQ9L9 Rg7ZISwIb0vRO9GxnlIqyBt1qoxx8lSNnTNtPhPaO0Y13yMUg7j+hxIIh9/ulVHDI4Pq edB2l/vT8ys3QYOdDswwqBASo9645LiLdpkrMqRpDGY7CXb3l24QB7zR94ZFVmJFGLma sGHA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j91-v6si14076401pld.14.2018.04.17.06.48.28; Tue, 17 Apr 2018 06:48:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753895AbeDQNqu (ORCPT + 99 others); Tue, 17 Apr 2018 09:46:50 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:55366 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753608AbeDQNp4 (ORCPT ); Tue, 17 Apr 2018 09:45:56 -0400 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w3HDi8rD020710; Tue, 17 Apr 2018 15:45:40 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2hb8hf8hgf-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 17 Apr 2018 15:45:38 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 0DC0D31; Tue, 17 Apr 2018 13:45:32 +0000 (GMT) Received: from Webmail-eu.st.com (gpxdag5node6.st.com [10.75.127.79]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id BE72B4EFB; Tue, 17 Apr 2018 13:45:32 +0000 (GMT) Received: from localhost (10.75.127.118) by GPXDAG5NODE6.st.com (10.75.127.79) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Tue, 17 Apr 2018 15:45:32 +0200 From: Fabrice Gasnier To: , CC: , , , , , Subject: [PATCH 0/4] Add STM32 timers to stm32mp157c Date: Tue, 17 Apr 2018 15:45:26 +0200 Message-ID: <1523972730-29240-1-git-send-email-fabrice.gasnier@st.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.75.127.118] X-ClientProxiedBy: GPXDAG7NODE6.st.com (10.75.127.85) To GPXDAG5NODE6.st.com (10.75.127.79) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2018-04-17_07:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This series adds support for STM32 timers to stm32mp157c. These timers can act PWM, trigger and/or encoder. Populate stm32mp157c SOC and ed1/ev1 boards. Fabrice Gasnier (4): ARM: dts: stm32: add timers support to stm32mp157c ARM: dts: stm32: add PWM pins used on stm32mp157c-ev1 board ARM: dts: stm32: add PWM and triggers on stm32mp157c-ev1 board ARM: dts: stm32: enable timer trigger 6 on stm32mp157c-ed1 arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 27 +++ arch/arm/boot/dts/stm32mp157c-ed1.dts | 7 + arch/arm/boot/dts/stm32mp157c-ev1.dts | 36 ++++ arch/arm/boot/dts/stm32mp157c.dtsi | 283 ++++++++++++++++++++++++++++++ 4 files changed, 353 insertions(+) -- 1.9.1