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[209.132.180.67]) by mx.google.com with ESMTP id a5-v6si13611013plp.196.2018.04.17.06.50.04; Tue, 17 Apr 2018 06:50:19 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753810AbeDQNsU (ORCPT + 99 others); Tue, 17 Apr 2018 09:48:20 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:57125 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753383AbeDQNpx (ORCPT ); Tue, 17 Apr 2018 09:45:53 -0400 Received: from pps.filterd (m0046037.ppops.net [127.0.0.1]) by mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w3HDi06t002075; Tue, 17 Apr 2018 15:45:35 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2hcptmyfn2-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 17 Apr 2018 15:45:35 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 582273F; Tue, 17 Apr 2018 13:45:35 +0000 (GMT) Received: from Webmail-eu.st.com (gpxdag5node6.st.com [10.75.127.79]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 400E84EFC; Tue, 17 Apr 2018 13:45:35 +0000 (GMT) Received: from localhost (10.75.127.119) by GPXDAG5NODE6.st.com (10.75.127.79) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Tue, 17 Apr 2018 15:45:34 +0200 From: Fabrice Gasnier To: , CC: , , , , , Subject: [PATCH 3/4] ARM: dts: stm32: add PWM and triggers on stm32mp157c-ev1 board Date: Tue, 17 Apr 2018 15:45:29 +0200 Message-ID: <1523972730-29240-4-git-send-email-fabrice.gasnier@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1523972730-29240-1-git-send-email-fabrice.gasnier@st.com> References: <1523972730-29240-1-git-send-email-fabrice.gasnier@st.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.75.127.119] X-ClientProxiedBy: GPXDAG4NODE5.st.com (10.75.127.75) To GPXDAG5NODE6.st.com (10.75.127.79) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2018-04-17_07:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org stm32mp157c evaluation board has TIM2_CH4, TIM8_CH4 and TIM12_CH1 available on GPIO expansion connector. Add PWM and associated triggers (for ADC/DAC) on these timers. Keep them disabled so these pins can be used as GPIOs by default. Signed-off-by: Fabrice Gasnier --- arch/arm/boot/dts/stm32mp157c-ev1.dts | 36 +++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts index 57e6dbc..2109558 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts @@ -19,3 +19,39 @@ serial0 = &uart4; }; }; + +&timers2 { + status = "disabled"; + pwm { + pinctrl-0 = <&pwm2_pins_a>; + pinctrl-names = "default"; + status = "okay"; + }; + timer@1 { + status = "okay"; + }; +}; + +&timers8 { + status = "disabled"; + pwm { + pinctrl-0 = <&pwm8_pins_a>; + pinctrl-names = "default"; + status = "okay"; + }; + timer@7 { + status = "okay"; + }; +}; + +&timers12 { + status = "disabled"; + pwm { + pinctrl-0 = <&pwm12_pins_a>; + pinctrl-names = "default"; + status = "okay"; + }; + timer@11 { + status = "okay"; + }; +}; -- 1.9.1