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[209.132.180.67]) by mx.google.com with ESMTP id n6-v6si1938205pla.12.2018.04.17.06.59.43; Tue, 17 Apr 2018 06:59:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=cdvqFTNg; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753932AbeDQN6P (ORCPT + 99 others); Tue, 17 Apr 2018 09:58:15 -0400 Received: from lelnx194.ext.ti.com ([198.47.27.80]:10112 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753072AbeDQN6N (ORCPT ); Tue, 17 Apr 2018 09:58:13 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id w3HDvpWp003556; Tue, 17 Apr 2018 08:57:51 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1523973471; bh=uB1aRiJzgTP7vceniyiz64FNq3tb/uuAY79GJ0/S01s=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=cdvqFTNgLObAesK000aW4RHV3p3UFmvivWlgc6Swm2V6H87fKKTVCtzA93ttgN+q7 +zRt/mX6JdBimiFZSIhikVLr15mEBnlReF11ct53oDprxSTE2JFZITkOIRY0eeEfw7 sTflqNAHeAFsGTMHuzjH4ZOhlc50vOILF6a0TwEo= Received: from DFLE101.ent.ti.com (dfle101.ent.ti.com [10.64.6.22]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w3HDvp5D005984; Tue, 17 Apr 2018 08:57:51 -0500 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Tue, 17 Apr 2018 08:57:50 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Tue, 17 Apr 2018 08:57:50 -0500 Received: from [172.24.190.172] (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w3HDvlbs032234; Tue, 17 Apr 2018 08:57:47 -0500 Subject: Re: [RESEND PATCH v2 2/4] memory: aemif: add support for board files To: Bartosz Golaszewski , Kevin Hilman , Russell King , Santosh Shilimkar CC: , , Bartosz Golaszewski References: <20180417102917.7794-1-brgl@bgdev.pl> <20180417102917.7794-3-brgl@bgdev.pl> From: Sekhar Nori Message-ID: Date: Tue, 17 Apr 2018 19:27:46 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: <20180417102917.7794-3-brgl@bgdev.pl> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tuesday 17 April 2018 03:59 PM, Bartosz Golaszewski wrote: > From: Bartosz Golaszewski > > Currently aemif is supported in two places separately. By the platform > driver in drivers/memory and by a hand crafted driver in mach-davinci. > > We want to drop the latter but also keep the legacy mode. Add support > for board files to the aemif driver. > > The new structure in platform data currently only contains the chip > select number, since currently existing users don't require anything > else, but it can be extended in the future. > > Signed-off-by: Bartosz Golaszewski > --- > drivers/memory/ti-aemif.c | 57 +++++++++++++++++--------- > include/linux/platform_data/ti-aemif.h | 9 ++++ > 2 files changed, 46 insertions(+), 20 deletions(-) > > diff --git a/drivers/memory/ti-aemif.c b/drivers/memory/ti-aemif.c > index 588e58d40d1b..27d2b076f465 100644 > --- a/drivers/memory/ti-aemif.c > +++ b/drivers/memory/ti-aemif.c > @@ -394,14 +401,24 @@ static int aemif_probe(struct platform_device *pdev) > } > > /* > - * Create a child devices explicitly from here to > - * guarantee that the child will be probed after the AEMIF timing > - * parameters are set. > + * Create a child devices explicitly from here to guarantee that the > + * child will be probed after the AEMIF timing parameters are set. > */ > - for_each_available_child_of_node(np, child_np) { > - ret = of_platform_populate(child_np, NULL, dev_lookup, dev); > - if (ret < 0) > - goto error; > + if (np) { > + for_each_available_child_of_node(np, child_np) { > + ret = of_platform_populate(child_np, NULL, > + dev_lookup, dev); > + if (ret < 0) > + goto error; > + } > + } else { > + for (i = 0; i < pdata->num_sub_devices; i++) { > + ret = platform_device_register(&pdata->sub_devices[i]); Before doing this can we make aemif device the parent of the sub_device? > + if (ret) { > + dev_warn(dev, "Error register sub device %s\n", > + pdata->sub_devices[i].name); > + } > + } > } > > return 0; > diff --git a/include/linux/platform_data/ti-aemif.h b/include/linux/platform_data/ti-aemif.h > index ac72e115093c..dfe8901128c9 100644 > --- a/include/linux/platform_data/ti-aemif.h > +++ b/include/linux/platform_data/ti-aemif.h > @@ -16,8 +16,17 @@ > > #include > > +struct aemif_abus_data { > + u32 cs; > +}; > + > struct aemif_platform_data { > struct of_dev_auxdata *dev_lookup; > + u32 cs_offset; > + struct aemif_abus_data *abus_data; > + size_t num_abus_data; > + struct platform_device *sub_devices; > + size_t num_sub_devices; It will be nice to add documentation for these members. Thanks, Sekhar