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From:   Alex Solomatnikov <sols@sifive.com>
Date:   Tue, 17 Apr 2018 13:35:27 -0700
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Subject: Re: [PATCH v3 1/2] perf: riscv: preliminary RISC-V support
To:     Alan Kao <alankao@andestech.com>
Cc:     Palmer Dabbelt <palmer@sifive.com>, Albert Ou <albert@sifive.com>,
        Peter Zijlstra <peterz@infradead.org>,
        Ingo Molnar <mingo@redhat.com>,
        Arnaldo Carvalho de Melo <acme@kernel.org>,
        Alexander Shishkin <alexander.shishkin@linux.intel.com>,
        Jiri Olsa <jolsa@redhat.com>,
        Namhyung Kim <namhyung@kernel.org>,
        Jonathan Corbet <corbet@lwn.net>,
        linux-riscv@lists.infradead.org, linux-doc@vger.kernel.org,
        linux-kernel@vger.kernel.org, Nick Hu <nickhu@andestech.com>,
        Greentime Hu <greentime@andestech.com>
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On Tue, Apr 17, 2018 at 1:38 AM, Alan Kao <alankao@andestech.com> wrote:

> +static inline void write_counter(int idx, u64 value)
> +{
> +       /* currently not supported */
> +}

CSR writes can be emulated: https://github.com/riscv/riscv-pk/pull/98

Or at least write_counter() should have BUG() or WARN_ONCE() or
something like that.