Received: by 10.192.165.156 with SMTP id m28csp1062162imm; Wed, 18 Apr 2018 03:27:41 -0700 (PDT) X-Google-Smtp-Source: AIpwx4/V6uF5UqabdmkvcaRXZwQs2GVj/MLcaS5uZ9X0GlaDbqwOc2eTyr4DeaPwPd4YSnyOsABk X-Received: by 10.98.127.144 with SMTP id a138mr1464917pfd.239.1524047261411; Wed, 18 Apr 2018 03:27:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1524047261; cv=none; d=google.com; s=arc-20160816; b=rf3hipzX/fJ3ImieryHq8hrP6u28Co78X8kfm2UtDxPYnkKee2T9o/y0yjOwPPB1ks Txr5UyRFf8mLoYsRk7xqOP13oIYyvy8rsL11LVvzmAxR1RMBM030VMIoV3dFOxzIh2/q nyPM4Nhyur42EA+77Ep8gQechIovk31bMaj199bpcfwqkepEPtUgHLW22QPFopOKm5VS VG909qoPBwbuH4Tvk7F9zYeMmFFTc0oNs+W9y8QtPDsjhAmFJ8uF14eWNfH3DD1TXTxH tgxH45sSrPHCgBq8YvvV1X3634kYKvTml1Q8x2d4O2O6W7L+pIY9924uoznMPWJ7AbnR Hw7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=+h61jfYP4nSUHb0jSx6/8bSmOBz840+PRPjI/MtGzLU=; b=Trxvu7BPq+Ky9ZtRdpUIJqJWbxeEnQCXqAmtVX5Yq/jwzSVmgkRcaijw3l2UsVp3AK DpO/igWdH9xluV14gG++bTswVogZscfs1QPCuN2sItJ02vd6w5b3WD1LVl+m6Wd+D7hV 96eWPe1xGx9Y90eTlSUp01z32SbNeZMEGehLvItZuo/9IVbbJSs4i4ct/qVJujZZ168q +05O3dy/vtMKT6pVh4OXWyffCtaLeyAgvzIxZuX1/7It0xh4iYjOvnwy1B6/yRjKfAFZ McdENpFGR60PYLNiIhG4xpjXU/skWlbnNrNyMLoa5x+qqDyBLlOgcIUe5qoDG7J+LYG3 aRvQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x6si796591pgv.430.2018.04.18.03.27.27; Wed, 18 Apr 2018 03:27:41 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753883AbeDRKZI (ORCPT + 99 others); Wed, 18 Apr 2018 06:25:08 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:9871 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1753843AbeDRKZF (ORCPT ); Wed, 18 Apr 2018 06:25:05 -0400 X-UUID: 3dae677c818244e2b30e2bddfe039b0b-20180418 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 2094205585; Wed, 18 Apr 2018 18:25:00 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Wed, 18 Apr 2018 18:24:58 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Wed, 18 Apr 2018 18:24:58 +0800 From: To: , , , , , , , CC: , , , , Sean Wang Subject: [PATCH v1 1/4] dt-bindings: gpu: mali-utgard: add mediatek,mt7623-mali compatible Date: Wed, 18 Apr 2018 18:24:53 +0800 Message-ID: <831e85ebdfdaba3c7b05ac8407a1584c20ba4a86.1524044917.git.sean.wang@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Sean Wang The MediaTek MT7623 SoC contains a Mali-450, so add a compatible for it and define its own vendor-specific properties. Signed-off-by: Sean Wang --- Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt index c1f65d1..e149995 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt @@ -20,6 +20,7 @@ Required properties: + rockchip,rk3228-mali + rockchip,rk3328-mali + stericsson,db8500-mali + + mediatek,mt7623-mali - reg: Physical base address and length of the GPU registers @@ -86,6 +87,14 @@ to specify one more vendor-specific compatible, among: * interrupt-names and interrupts: + combined: combined interrupt of all of the above lines + - mediatek,mt7623-mali + Required properties: + * resets: phandle to the reset line for the GPU + * mediatek,larb: phandle pointed to the local arbiter used to control the + access to external memory on the SoC. + see Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt + for details + Example: mali: gpu@1c40000 { -- 2.7.4