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To:     Amit Nischal <anischal@codeaurora.org>,
        Manu Gautam <mgautam@codeaurora.org>
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        Doug Anderson <dianders@chromium.org>
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Subject: Re: [PATCH v3 3/3] clk: qcom: Add Global Clock controller (GCC) driver for
 SDM845
Date:   Wed, 18 Apr 2018 16:31:45 -0700
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Quoting Manu Gautam (2018-04-18 09:38:41)
> Hi Amit,
> 
> 
> On 4/18/2018 6:33 PM, Amit Nischal wrote:
> >>> +       /* Disable the GPLL0 active input to MMSS and GPU via MISC registers */
> >>> +       regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3);
> >>> +       regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
> >>
> >> I think we'll have to throw in the pipe clk branch stuff in here too?
> >> And then drop the pipe clks from the driver?
> >
> > All the USB pipe clocks would be taken care. The PCIE pipe branch
> > clocks would have to be explicitly disabled so as to retain the
> > memory logic. Otherwise, it would lead to memory corruption in case
> > the external source is directly disabled without disabling the branch clock. 
> 
> PHY driver is same for both USB and PCIE and both PHYs use pipe_clk.
> If there is indeed some limitation and pipe_clk cant be left enabled
> always then I will suggest to not change pipe_clk handling for USB as well.
> 

Right. This is concerning if we have a half way solution.

Just to clarify my understanding, are you saying that the pcie pipe clks
are also tied to the memory logic and so toggling them on/off is used to
reset the memories inside the phy? Or the memories inside the
controller? What is the pipe clk clocking in these cases?