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[209.132.180.67]) by mx.google.com with ESMTP id y185si2642296pgd.316.2018.04.19.02.01.59; Thu, 19 Apr 2018 02:02:13 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751293AbeDSJAt convert rfc822-to-8bit (ORCPT + 99 others); Thu, 19 Apr 2018 05:00:49 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:1741 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750735AbeDSJAr (ORCPT ); Thu, 19 Apr 2018 05:00:47 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Thu, 19 Apr 2018 02:00:59 -0700 Received: from HQMAIL104.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Thu, 19 Apr 2018 02:00:46 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Thu, 19 Apr 2018 02:00:46 -0700 Received: from BGMAIL104.nvidia.com (10.25.59.13) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 19 Apr 2018 09:00:44 +0000 Received: from BGMAIL102.nvidia.com (10.25.59.11) by bgmail104.nvidia.com (10.25.59.13) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 19 Apr 2018 09:00:41 +0000 Received: from BGMAIL102.nvidia.com ([::1]) by bgmail102.nvidia.com ([fe80::250a:5992:4657:28e%20]) with mapi id 15.00.1347.000; Thu, 19 Apr 2018 09:00:41 +0000 From: Bhadram Varka To: Jisheng Zhang CC: Andrew Lunn , Florian Fainelli , "David S. Miller" , "netdev@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Jingju Hou Subject: RE: [PATCH] net: phy: marvell: clear wol event before setting it Thread-Topic: [PATCH] net: phy: marvell: clear wol event before setting it Thread-Index: AQHT17Tmskie4f0tkky4KxMjyNmTQKQHwlIAgAAGJICAAADlUA== Date: Thu, 19 Apr 2018 09:00:40 +0000 Message-ID: References: <20180419160232.519d15be@xhacker.debian> <96e77eac86794bef9a5b772147527c67@bgmail102.nvidia.com> <20180419165351.5388021e@xhacker.debian> In-Reply-To: <20180419165351.5388021e@xhacker.debian> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.24.193.52] MIME-Version: 1.0 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, > -----Original Message----- > From: Jisheng Zhang > Sent: Thursday, April 19, 2018 2:24 PM > To: Bhadram Varka > Cc: Andrew Lunn ; Florian Fainelli ; > David S. Miller ; netdev@vger.kernel.org; linux- > kernel@vger.kernel.org; Jingju Hou > Subject: Re: [PATCH] net: phy: marvell: clear wol event before setting it > > Hi, > > On Thu, 19 Apr 2018 08:38:45 +0000 Bhadram Varka wrote: > > > Hi, > > > > > -----Original Message----- > > > From: netdev-owner@vger.kernel.org On > > > Behalf Of Jisheng Zhang > > > Sent: Thursday, April 19, 2018 1:33 PM > > > To: Andrew Lunn ; Florian Fainelli > > > ; David S. Miller > > > Cc: netdev@vger.kernel.org; linux-kernel@vger.kernel.org; Jingju Hou > > > > > > Subject: [PATCH] net: phy: marvell: clear wol event before setting > > > it > > > > > > From: Jingju Hou > > > > > > If WOL event happened once, the LED[2] interrupt pin will not be > > > cleared unless reading the CSISR register. So clear the WOL event before > enabling it. > > > > > > Signed-off-by: Jingju Hou > > > Signed-off-by: Jisheng Zhang > > > --- > > > drivers/net/phy/marvell.c | 9 +++++++++ > > > 1 file changed, 9 insertions(+) > > > > > > diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c > > > index c22e8e383247..b6abe1cbc84b 100644 > > > --- a/drivers/net/phy/marvell.c > > > +++ b/drivers/net/phy/marvell.c > > > @@ -115,6 +115,9 @@ > > > /* WOL Event Interrupt Enable */ > > > #define MII_88E1318S_PHY_CSIER_WOL_EIE BIT(7) > > > > > > +/* Copper Specific Interrupt Status Register */ > > > +#define MII_88E1318S_PHY_CSISR 0x13 > > > + > > > > There is already macro to represent this register - MII_M1011_IEVENT. Do we > need this macro ? > > Good point. Will use MII_M1011_IEVENT instead in v2. > > > > > > /* LED Timer Control Register */ > > > #define MII_88E1318S_PHY_LED_TCR 0x12 > > > #define MII_88E1318S_PHY_LED_TCR_FORCE_INT BIT(15) > > > @@ -1393,6 +1396,12 @@ static int m88e1318_set_wol(struct phy_device > > > *phydev, > > > if (err < 0) > > > goto error; > > > > > > + /* If WOL event happened once, the LED[2] interrupt pin > > > + * will not be cleared unless reading the CSISR register. > > > + * So clear the WOL event first before enabling it. > > > + */ > > > + phy_read(phydev, MII_88E1318S_PHY_CSISR); > > > > This part of the operation already taken care by ack_interrupt and > > did_interrupt [....] .ack_interrupt = &marvell_ack_interrupt, > > .did_interrupt = &m88e1121_did_interrupt, [...] > > > > If at all WOL event occurred marvell_ack_interrupt will take care of clearing the > interrupt status register. > > Am I missing anything here ? > > If there's no valid irq for phy, the ack_interrupt/did_interrupt won't be called. Which means that the PHY is not having Interrupt pin ? Generally through PHY interrupt will wake up the system right. If there is no interrupt pin then how the system will wake up the from suspend for the magic packet.? Thanks!