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[209.132.180.67]) by mx.google.com with ESMTP id 16si4868860pfh.354.2018.04.20.00.14.30; Fri, 20 Apr 2018 00:14:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@ffwll.ch header.s=google header.b=E/BvNcLG; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753854AbeDTHNT (ORCPT + 99 others); Fri, 20 Apr 2018 03:13:19 -0400 Received: from mail-wr0-f171.google.com ([209.85.128.171]:45854 "EHLO mail-wr0-f171.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753529AbeDTHNQ (ORCPT ); Fri, 20 Apr 2018 03:13:16 -0400 Received: by mail-wr0-f171.google.com with SMTP id u11-v6so20084273wri.12 for ; Fri, 20 Apr 2018 00:13:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=sender:date:from:to:cc:subject:message-id:mail-followup-to :references:mime-version:content-disposition:in-reply-to:user-agent; bh=0eEUpR1DeKBYY5H+/GPk/fmT4JyQ81yMGYtbrkdman8=; b=E/BvNcLGPs/M0fs3sdBAcaitZdqBl5kdaZDq+4n1hjpPTRsDcdjkmEw8hQPdLSaKv/ maS5ifx0VOf+V24Uov67HD6lgtvadiqJyISd33Z4AHgb4jKBlUrzCkqivEXGMQzgZNTH 9TpEndjI58TXK5O1HoF9nEhe6rkQxwMy+1rMg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:date:from:to:cc:subject:message-id :mail-followup-to:references:mime-version:content-disposition :in-reply-to:user-agent; bh=0eEUpR1DeKBYY5H+/GPk/fmT4JyQ81yMGYtbrkdman8=; b=mjOp8VIqsaHOw+xEh4JXvf6tLyM4wPKzqeT8uQ7ugILJ00KC2JRNr6DimBxhSZcvJ+ GRLrGWFybpgqhy+uWxmtmt8bUuioBx29lvCm7PczsTKF1irdMkJ7gOQjKi88aPIGaQRr h58lHdh5dl7I0wUa85gGJOwKT+QtnbAQRz1S1yeGqT5ME1QTvxtTlQFMB4y3G5+vrii8 +ez8fWxp00NIdyjdvwhno2WZx2vK8ixP7KiVTpFhqGsksuuGGBoyLiznFuoLiyj7TqA+ F4ZMT1JYJmZjFaSpLa19EPQwISLET0QCapmX2Ntmme6lx13mIzm7iG3/tu8ibizT+IOu 5owg== X-Gm-Message-State: ALQs6tBiIIeUmFxd1iI3NkB7TSrfo/r1WQZMCuBlobP9DudXStwTlbBS 33THSTjuC4cYSFhVYi+xQifmGQ== X-Received: by 10.80.132.99 with SMTP id 90mr12711801edp.61.1524208395384; Fri, 20 Apr 2018 00:13:15 -0700 (PDT) Received: from phenom.ffwll.local ([2a02:168:5635:0:39d2:f87e:2033:9f6]) by smtp.gmail.com with ESMTPSA id d89sm3093320edc.41.2018.04.20.00.13.13 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 20 Apr 2018 00:13:14 -0700 (PDT) Date: Fri, 20 Apr 2018 09:13:12 +0200 From: Daniel Vetter To: Christoph Hellwig Cc: Daniel Vetter , Jerome Glisse , Christian =?iso-8859-1?Q?K=F6nig?= , "moderated list:DMA BUFFER SHARING FRAMEWORK" , "open list:DMA BUFFER SHARING FRAMEWORK" , dri-devel , amd-gfx list , Linux Kernel Mailing List , Logan Gunthorpe , Dan Williams Subject: Re: [PATCH 4/8] dma-buf: add peer2peer flag Message-ID: <20180420071312.GF31310@phenom.ffwll.local> Mail-Followup-To: Christoph Hellwig , Jerome Glisse , Christian =?iso-8859-1?Q?K=F6nig?= , "moderated list:DMA BUFFER SHARING FRAMEWORK" , "open list:DMA BUFFER SHARING FRAMEWORK" , dri-devel , amd-gfx list , Linux Kernel Mailing List , Logan Gunthorpe , Dan Williams References: <20180325110000.2238-1-christian.koenig@amd.com> <20180325110000.2238-4-christian.koenig@amd.com> <20180329065753.GD3881@phenom.ffwll.local> <8b823458-8bdc-3217-572b-509a28aae742@gmail.com> <20180403090909.GN3881@phenom.ffwll.local> <20180403170645.GB5935@redhat.com> <20180403180832.GZ3881@phenom.ffwll.local> <20180416123937.GA9073@infradead.org> <20180419081657.GA16735@infradead.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20180419081657.GA16735@infradead.org> X-Operating-System: Linux phenom 4.15.0-1-amd64 User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Apr 19, 2018 at 01:16:57AM -0700, Christoph Hellwig wrote: > On Mon, Apr 16, 2018 at 03:38:56PM +0200, Daniel Vetter wrote: > > We've broken that assumption in i915 years ago. Not struct page backed > > gpu memory is very real. > > > > Of course we'll never feed such a strange sg table to a driver which > > doesn't understand it, but allowing sg_page == NULL works perfectly > > fine. At least for gpu drivers. > > For GPU drivers on x86 with no dma coherency problems, sure. But not > all the world is x86. We already have problems due to dmabugs use > of the awkward get_sgtable interface (see the common on > arm_dma_get_sgtable that I fully agree with), and doing this for memory > that doesn't have a struct page at all will make things even worse. x86 dma isn't coherent either, if you're a GPU :-) Flushing gpu caches tends to be too expensive, so there's pci-e support and chipset support to forgo it. Plus drivers flushing caches themselves. The dma_get_sgtable thing is indeed fun, right solution would probably be to push the dma-buf export down into the dma layer. The comment for arm_dma_get_sgtable is also not a realy concern, because dma-buf also abstracts away the flushing (or well is supposed to), so there really shouldn't be anyone calling the streaming apis on the returned sg table. That's why dma-buf gives you an sg table that's mapped already. > > If that's not acceptable then I guess we could go over the entire tree > > and frob all the gpu related code to switch over to a new struct > > sg_table_might_not_be_struct_page_backed, including all the other > > functions we added over the past few years to iterate over sg tables. > > But seems slightly silly, given that sg tables seem to do exactly what > > we need. > > It isn't silly. We will have to do some surgery like that anyway > because the current APIs don't work. So relax, sit back and come up > with an API that solves the existing issues and serves us well in > the future. So we should just implement a copy of sg table for dma-buf, since I still think it does exactly what we need for gpus? Yes there's a bit a layering violation insofar that drivers really shouldn't each have their own copy of "how do I convert a piece of dma memory into dma-buf", but that doesn't render the interface a bad idea. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch