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[209.132.180.67]) by mx.google.com with ESMTP id p85si5008423pfk.77.2018.04.20.01.36.42; Fri, 20 Apr 2018 01:36:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@infradead.org header.s=merlin.20170209 header.b=XWK9SZrh; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754168AbeDTIfe (ORCPT + 99 others); Fri, 20 Apr 2018 04:35:34 -0400 Received: from merlin.infradead.org ([205.233.59.134]:47276 "EHLO merlin.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753957AbeDTIfd (ORCPT ); Fri, 20 Apr 2018 04:35:33 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=merlin.20170209; h=In-Reply-To:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=Y0aGGhDxaysGaUKaDBExEi4qTj9pjmj1ba6mP7fbZSQ=; b=XWK9SZrhVSP/O/XE6YbGzCMtz w2WnVKp+hS3Hz5tx8eC/RPzXN4byU5+MIr4gKNkpzdZj+oegJduDY3Xj5AgMmCAcD6tWyCj88x9AY mLF9paqb4d44XOU3VrSoJpWcEpDw4loOVgJKu+8smPyUO0vbqOFm6LIEPoWtMLG5QjDQfWQ06ympk ZU78U/27HX+9t6/IKquT0Zs3PO2kGGV19aFi1WDOve+hkmibDw1MaRX34eNqSnHD18KQJTFLqBU2m 9+USKJ6mboFmc0HLCgs5AOivk46E+O5Ps/l1b3MvO8zHgAIWAXXMukwFEOS37S016Qk/L0FjujLdz 2WRWfxl3Q==; Received: from j217100.upc-j.chello.nl ([24.132.217.100] helo=hirez.programming.kicks-ass.net) by merlin.infradead.org with esmtpsa (Exim 4.90_1 #2 (Red Hat Linux)) id 1f9RVq-00024I-Ub; Fri, 20 Apr 2018 08:35:23 +0000 Received: by hirez.programming.kicks-ass.net (Postfix, from userid 1000) id 7E9C52028838D; Fri, 20 Apr 2018 10:35:21 +0200 (CEST) Date: Fri, 20 Apr 2018 10:35:21 +0200 From: Peter Zijlstra To: Stephane Eranian Cc: LKML , Jiri Olsa , Arnaldo Carvalho de Melo , mingo@elte.hu, Andi Kleen , Vince Weaver Subject: Re: [RFC] perf/core: what is exclude_idle supposed to do Message-ID: <20180420083521.GF4064@hirez.programming.kicks-ass.net> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.9.3 (2018-01-21) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Apr 16, 2018 at 10:04:53PM +0000, Stephane Eranian wrote: > Hi, > > I am trying to understand what the exclude_idle event attribute is supposed > to accomplish. > As per the definition in the header file: > > exclude_idle : 1, /* don't count when idle */ > > Naively, I thought it would simply stop the event when running in the > context of the idle task (swapper, pid 0) on any CPU. That would seem to > match the succinct description. > > However, running a simple: > > $ perf record -a -e cycles:I sleep 5 > perf_event_attr: > sample_type IP|TID|TIME|CPU|PERIOD > read_format TOTAL_TIME_ENABLED|TOTAL_TIME_RUNNING|ID > exclude_idle 1 > > on an idle machine, showed me that this is not what is actually happening: > $ perf script > swapper 0 [000] 1132634.287442: 1 cycles:I: > ffffffff8100b1fb __intel_pmu_enable_all.isra.17 ([kernel.kallsyms]) > swapper 0 [001] 1132634.287498: 1 cycles:I: > ffffffff8100b1fb __intel_pmu_enable_all.isra.17 ([kernel.kallsyms]) > > > After looking at the code, it all made sense, it seems to current > implementation is only relevant for sw events. I don't understand why. > > I am left wondering what is the goal of exclude_idle? A "git grep exclude_idle" seems to suggest powerpc/arm have it immplemented for their PMU. If we then look at commit: 2743a5b0fa6f ("perfcounters: provide expansion room in the ABI") It was Paul who introduced the bit. So I'm thinking that if x86 doesn't implement it, we should at least error out on it. Of course, so far we've allowed it, so who knows what all will break if we start asserting that :/