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[209.132.180.67]) by mx.google.com with ESMTP id m9-v6si5429496pll.67.2018.04.20.03.29.41; Fri, 20 Apr 2018 03:29:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754658AbeDTK2d (ORCPT + 99 others); Fri, 20 Apr 2018 06:28:33 -0400 Received: from 9pmail.ess.barracuda.com ([64.235.154.211]:39441 "EHLO 9pmail.ess.barracuda.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754458AbeDTK2b (ORCPT ); Fri, 20 Apr 2018 06:28:31 -0400 Received: from MIPSMAIL01.mipstec.com (mailrelay.mips.com [12.201.5.28]) by mx1401.ess.rzc.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NO); Fri, 20 Apr 2018 10:27:23 +0000 Received: from mredfearn-linux.mipstec.com (192.168.155.41) by MIPSMAIL01.mipstec.com (10.20.43.31) with Microsoft SMTP Server (TLS) id 14.3.361.1; Fri, 20 Apr 2018 03:25:16 -0700 From: Matt Redfearn To: James Hogan , Ralf Baechle , Florian Fainelli CC: , Matt Redfearn , Namhyung Kim , "Maciej W. Rozycki" , Peter Zijlstra , , "Paul Burton" , Ingo Molnar , Jiri Olsa , Alexander Shishkin , Arnaldo Carvalho de Melo Subject: [PATCH v3 7/7] MIPS: perf: Fix BMIPS5000 system mode counting Date: Fri, 20 Apr 2018 11:23:09 +0100 Message-ID: <1524219789-31241-8-git-send-email-matt.redfearn@mips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1524219789-31241-1-git-send-email-matt.redfearn@mips.com> References: <1524219789-31241-1-git-send-email-matt.redfearn@mips.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [192.168.155.41] X-BESS-ID: 1524219945-321457-10557-42113-6 X-BESS-VER: 2018.5-r1804181636 X-BESS-Apparent-Source-IP: 12.201.5.28 X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.192194 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND X-BESS-BRTS-Status: 1 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When perf is used in system mode, i.e. specifying a set of CPUs to count (perf -a -C cpu), event->cpu is set to the CPU number on which events should be counted. The current BMIPS500 variation of mipsxx_pmu_enable_event only over sets the counter to count the current CPU, so system mode does not work. Fix this by removing this BMIPS5000 specific path and integrating it with the generic one. Since BMIPS5000 uses specific extensions to the perf control register, different fields must be set up to count the relevant CPU. Signed-off-by: Matt Redfearn --- Changes in v3: None Changes in v2: New patch to fix BMIPS5000 system mode perf. Florian, I don't have access to a BMIPS5000 board, but from code inspection only I suspect this patch is necessary to have system mode work. If someone could test that would be appreciated. --- arch/mips/include/asm/mipsregs.h | 1 + arch/mips/kernel/perf_event_mipsxx.c | 17 ++++++----------- 2 files changed, 7 insertions(+), 11 deletions(-) diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index a4baaaa02bc8..3e1fbb7aaa2a 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -735,6 +735,7 @@ #define MIPS_PERFCTRL_MT_EN_TC (_ULCAST_(2) << 20) /* PerfCnt control register MT extensions used by BMIPS5000 */ +#define BRCM_PERFCTRL_VPEID(v) (_ULCAST_(1) << (12 + v)) #define BRCM_PERFCTRL_TC (_ULCAST_(1) << 30) /* PerfCnt control register MT extensions used by Netlogic XLR */ diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c index 5b8811643e60..77d7167e303b 100644 --- a/arch/mips/kernel/perf_event_mipsxx.c +++ b/arch/mips/kernel/perf_event_mipsxx.c @@ -364,16 +364,7 @@ static void mipsxx_pmu_enable_event(struct hw_perf_event *evt, int idx) /* Make sure interrupt enabled. */ MIPS_PERFCTRL_IE; -#ifdef CONFIG_CPU_BMIPS5000 - { - /* enable the counter for the calling thread */ - unsigned int vpe_id; - - vpe_id = smp_processor_id() & MIPS_CPUID_TO_COUNTER_MASK; - cpuc->saved_ctrl[idx] |= BIT(12 + vpe_id) | BRCM_PERFCTRL_TC; - } -#else -#ifdef CONFIG_MIPS_MT_SMP +#if defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_CPU_BMIPS5000) if (range > V) { /* The counter is processor wide. Set it up to count all TCs. */ pr_debug("Enabling perf counter for all TCs\n"); @@ -390,12 +381,16 @@ static void mipsxx_pmu_enable_event(struct hw_perf_event *evt, int idx) */ cpu = (event->cpu >= 0) ? event->cpu : smp_processor_id(); +#if defined(CONFIG_CPU_BMIPS5000) + ctrl = BRCM_PERFCTRL_VPEID(cpu & MIPS_CPUID_TO_COUNTER_MASK); + ctrl |= BRCM_PERFCTRL_TC; +#else ctrl = M_PERFCTL_VPEID(cpu_vpe_id(&cpu_data[cpu])); ctrl |= M_TC_EN_VPE; +#endif cpuc->saved_ctrl[idx] |= ctrl; pr_debug("Enabling perf counter for CPU%d\n", cpu); } -#endif /* CONFIG_CPU_BMIPS5000 */ /* * We do not actually let the counter run. Leave it until start(). */ -- 2.7.4