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[209.132.180.67]) by mx.google.com with ESMTP id x7si4950083pge.559.2018.04.20.06.12.18; Fri, 20 Apr 2018 06:12:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@xff.cz header.s=mail header.b=K5ihy9ZK; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=xff.cz Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754955AbeDTNKa (ORCPT + 99 others); Fri, 20 Apr 2018 09:10:30 -0400 Received: from vps.xff.cz ([195.181.215.36]:40868 "EHLO vps.xff.cz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754800AbeDTNK3 (ORCPT ); Fri, 20 Apr 2018 09:10:29 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=xff.cz; s=mail; t=1524229827; bh=yqg7YPaBjLW4PqCc5zKyy9dN6VvBMZEFup85ryD9+w4=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=K5ihy9ZKxuNuFC8Yct3Um053fz7Pu7eRxfugQj/Ojf/V+rtyyR3KsX30aqRx9s5on UgH4h8/0QpHML6m+4p+HLnz8TfNUAk7X0Cbx04dDccbZQWxPz+kLYcBG128w9tuXhE HiTCrsRwlSN9uyE/GcXwiL4nc/ozFqYtpJKhb0Fc= Date: Fri, 20 Apr 2018 15:10:26 +0200 From: =?utf-8?Q?Ond=C5=99ej?= Jirman To: Giulio Benetti Cc: Chen-Yu Tsai , Maxime Ripard , David Airlie , linux-kernel , dri-devel , linux-arm-kernel Subject: Re: [v2] drm/sun4i: add lvds mode_valid function Message-ID: <20180420131026.vbg3qgrj26egw5s2@core> Mail-Followup-To: Giulio Benetti , Chen-Yu Tsai , Maxime Ripard , David Airlie , linux-kernel , dri-devel , linux-arm-kernel References: <1520940019-68977-1-git-send-email-giulio.benetti@micronovasrl.com> <20180419133421.6fx3whge7h364vd3@core> <129dfeb0-0962-608d-370e-277a3acce7ca@micronovasrl.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <129dfeb0-0962-608d-370e-277a3acce7ca@micronovasrl.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hello, On Thu, Apr 19, 2018 at 04:02:08PM +0200, Giulio Benetti wrote: > Hi everybody, > > Il 19/04/2018 15:36, Chen-Yu Tsai ha scritto: > > On Thu, Apr 19, 2018 at 9:34 PM, Ondřej Jirman > > wrote: > > > Hello Giulio, > > > > > > this patch breaks LVDS output on A83T. Without it, modesetting works, > > > with it there's no output. > > > > > > Some more info below... > > > > > > On Tue, Mar 13, 2018 at 12:20:19PM +0100, Giulio Benetti wrote: > > > > mode_valid function is missing for lvds. > > > > > > > > Add it making it pointed by encoder helper functions. > > > > > > > > Signed-off-by: Giulio Benetti > > > > --- > > > > drivers/gpu/drm/sun4i/sun4i_lvds.c | 55 ++++++++++++++++++++++++++++++++++++++ > > > > 1 file changed, 55 insertions(+) > > > > > > > > diff --git a/drivers/gpu/drm/sun4i/sun4i_lvds.c b/drivers/gpu/drm/sun4i/sun4i_lvds.c > > > > index be3f14d..bffff4c 100644 > > > > --- a/drivers/gpu/drm/sun4i/sun4i_lvds.c > > > > +++ b/drivers/gpu/drm/sun4i/sun4i_lvds.c > > > > @@ -94,9 +94,64 @@ static void sun4i_lvds_encoder_disable(struct drm_encoder *encoder) > > > > } > > > > } > > > > > > > > +static enum drm_mode_status sun4i_lvds_encoder_mode_valid(struct drm_encoder *crtc, > > > > + const struct drm_display_mode *mode) > > > > +{ > > > > + struct sun4i_lvds *lvds = drm_encoder_to_sun4i_lvds(crtc); > > > > + struct sun4i_tcon *tcon = lvds->tcon; > > > > + u32 hsync = mode->hsync_end - mode->hsync_start; > > > > + u32 vsync = mode->vsync_end - mode->vsync_start; > > > > + unsigned long rate = mode->clock * 1000; > > > > + long rounded_rate; > > > > + > > > > + DRM_DEBUG_DRIVER("Validating modes...\n"); > > > > + > > > > + if (hsync < 1) > > > > + return MODE_HSYNC_NARROW; > > > > + > > > > + if (hsync > 0x3ff) > > > > + return MODE_HSYNC_WIDE; > > > > + > > > > + if ((mode->hdisplay < 1) || (mode->htotal < 1)) > > > > + return MODE_H_ILLEGAL; > > > > + > > > > + if ((mode->hdisplay > 0x7ff) || (mode->htotal > 0xfff)) > > > > + return MODE_BAD_HVALUE; > > > > + > > > > + DRM_DEBUG_DRIVER("Horizontal parameters OK\n"); > > > > + > > > > + if (vsync < 1) > > > > + return MODE_VSYNC_NARROW; > > > > + > > > > + if (vsync > 0x3ff) > > > > + return MODE_VSYNC_WIDE; > > > > + > > > > + if ((mode->vdisplay < 1) || (mode->vtotal < 1)) > > > > + return MODE_V_ILLEGAL; > > > > + > > > > + if ((mode->vdisplay > 0x7ff) || (mode->vtotal > 0xfff)) > > > > + return MODE_BAD_VVALUE; > > > > + > > > > + DRM_DEBUG_DRIVER("Vertical parameters OK\n"); > > > > + > > > > + tcon->dclk_min_div = 7; > > > > + tcon->dclk_max_div = 7; > > > > > > Why would validation function change any state anywhere? > > > > > > > + rounded_rate = clk_round_rate(tcon->dclk, rate); > > > > > > The issue is here, on A83T TBS A711 tablet, I get... > > > > > > sun4i-tcon 1c0c000.lcd-controller: XXX: hsync=20 hdisplay=1024 htotal=1384 > > > vsync=5 vdisplay=600 vtotal=640 rate=52000000 rounded_rate=51857142 > > > > > > > + if (rounded_rate < rate) > > > > + return MODE_CLOCK_LOW; > > > > + > > > > + if (rounded_rate > rate) > > > > + return MODE_CLOCK_HIGH; > > > > > > ... while the previous conditions require an exact match for some reason. > > > > > > But HW works fine without an exact rate match. Why is exact match required here? > > > > This thread might provide some more info, though we could never get an > > agreement. > > > > https://patchwork.kernel.org/patch/9446385/ > > Thanks for pointing that Thread ChenYu. > So the only chance is to trim frequency according to encoder capabilities. > I agree to block when encoder can't provide frequency specified, > otherwise you could drive you panel at the near the lowest(highest) > frequency and get out of limits for a few without knowing it. When I set the range of pixel clock frequencies on simple-panel connected to this encoder, the check still fails, so there's something not working there as expected. This check is only called once with a typical frequency. I guess drm doesn't implement clock-frequency range on panels. But I haven't looked. I can set the exact frequency that the SoC can provide on the simple-panel, but that's a bit of a hack. regards, o. > Best regards > > -- > Giulio Benetti