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[209.132.180.67]) by mx.google.com with ESMTP id y87si12879770pfi.141.2018.04.24.00.57.14; Tue, 24 Apr 2018 00:57:28 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756660AbeDXHz0 (ORCPT + 99 others); Tue, 24 Apr 2018 03:55:26 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:19306 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756630AbeDXHzP (ORCPT ); Tue, 24 Apr 2018 03:55:15 -0400 Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w3O7rhZO025029; Tue, 24 Apr 2018 09:55:10 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2hftrwq4tv-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 24 Apr 2018 09:55:10 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id E87C956; Tue, 24 Apr 2018 07:55:09 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas24.st.com [10.75.90.94]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id C016F1154; Tue, 24 Apr 2018 07:55:09 +0000 (GMT) Received: from SAFEX1HUBCAS22.st.com (10.75.90.93) by Safex1hubcas24.st.com (10.75.90.94) with Microsoft SMTP Server (TLS) id 14.3.361.1; Tue, 24 Apr 2018 09:55:09 +0200 Received: from localhost (10.201.23.68) by Webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.361.1; Tue, 24 Apr 2018 09:55:09 +0200 From: yannick fertre To: Philippe Cornu , Alexandre Torgue , Rob Herring , Mark Rutland , , , Loic Pallardy , "Gerald Baeza" , Patrice Chotard , "Kamel Kholti" CC: Benjamin Gaignard Subject: [PATCH v1 2/2] ARM: dts: stm32: add dsi support on stm32mp157c Date: Tue, 24 Apr 2018 09:54:48 +0200 Message-ID: <1524556488-5404-3-git-send-email-yannick.fertre@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1524556488-5404-1-git-send-email-yannick.fertre@st.com> References: <1524556488-5404-1-git-send-email-yannick.fertre@st.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.201.23.68] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2018-04-24_01:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add dsi support on stm32mp157c Signed-off-by: yannick fertre --- arch/arm/boot/dts/stm32mp157c.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index af6cc48..c61cb6d 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -168,6 +168,16 @@ #reset-cells = <1>; }; + dsi: dsi@5a000000 { + compatible = "st,stm32-dsi"; + reg = <0x5a000000 0x800>; + clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>; + clock-names = "pclk", "ref", "px_clk"; + resets = <&rcc DSI_R>; + reset-names = "apb"; + status = "disabled"; + }; + ltdc: display-controller@5a001000 { compatible = "st,stm32-ltdc"; reg = <0x5a001000 0x400>; -- 1.9.1