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[209.132.180.67]) by mx.google.com with ESMTP id p8si10943518pgn.406.2018.04.24.00.57.19; Tue, 24 Apr 2018 00:57:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756646AbeDXHzV (ORCPT + 99 others); Tue, 24 Apr 2018 03:55:21 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:1027 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756604AbeDXHzO (ORCPT ); Tue, 24 Apr 2018 03:55:14 -0400 Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w3O7rhVO025032; Tue, 24 Apr 2018 09:55:09 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2hftrwq4tb-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 24 Apr 2018 09:55:09 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 799BE31; Tue, 24 Apr 2018 07:55:08 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas23.st.com [10.75.90.46]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 634001154; Tue, 24 Apr 2018 07:55:08 +0000 (GMT) Received: from SAFEX1HUBCAS22.st.com (10.75.90.93) by SAFEX1HUBCAS23.st.com (10.75.90.46) with Microsoft SMTP Server (TLS) id 14.3.361.1; Tue, 24 Apr 2018 09:55:08 +0200 Received: from localhost (10.201.23.68) by Webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.361.1; Tue, 24 Apr 2018 09:55:04 +0200 From: yannick fertre To: Philippe Cornu , Alexandre Torgue , Rob Herring , Mark Rutland , , , Loic Pallardy , "Gerald Baeza" , Patrice Chotard , "Kamel Kholti" CC: Benjamin Gaignard Subject: [PATCH v1 1/2] ARM: dts: stm32: add ltdc support on stm32mp157c Date: Tue, 24 Apr 2018 09:54:47 +0200 Message-ID: <1524556488-5404-2-git-send-email-yannick.fertre@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1524556488-5404-1-git-send-email-yannick.fertre@st.com> References: <1524556488-5404-1-git-send-email-yannick.fertre@st.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.201.23.68] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2018-04-24_01:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for the display controller ltdc. Signed-off-by: yannick fertre --- arch/arm/boot/dts/stm32mp157c.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index bc3eddc..af6cc48 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -5,6 +5,7 @@ */ #include #include +#include / { #address-cells = <1>; @@ -167,6 +168,17 @@ #reset-cells = <1>; }; + ltdc: display-controller@5a001000 { + compatible = "st,stm32-ltdc"; + reg = <0x5a001000 0x400>; + interrupts = , + ; + clocks = <&rcc LTDC_PX>; + clock-names = "lcd"; + resets = <&rcc LTDC_R>; + status = "disabled"; + }; + usart1: serial@5c000000 { compatible = "st,stm32h7-uart"; reg = <0x5c000000 0x400>; -- 1.9.1