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[209.132.180.67]) by mx.google.com with ESMTP id g11si10935577pgq.329.2018.04.24.00.57.45; Tue, 24 Apr 2018 00:58:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756574AbeDXHyi (ORCPT + 99 others); Tue, 24 Apr 2018 03:54:38 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:45644 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1756072AbeDXHyd (ORCPT ); Tue, 24 Apr 2018 03:54:33 -0400 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w3O7rnfa029254; Tue, 24 Apr 2018 09:54:28 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2hfte8y64q-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 24 Apr 2018 09:54:28 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 3120438; Tue, 24 Apr 2018 07:54:28 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas23.st.com [10.75.90.46]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 164D91159; Tue, 24 Apr 2018 07:54:28 +0000 (GMT) Received: from SAFEX1HUBCAS22.st.com (10.75.90.93) by SAFEX1HUBCAS23.st.com (10.75.90.46) with Microsoft SMTP Server (TLS) id 14.3.361.1; Tue, 24 Apr 2018 09:54:28 +0200 Received: from localhost (10.201.23.68) by Webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.361.1; Tue, 24 Apr 2018 09:54:27 +0200 From: yannick fertre To: Philippe Cornu , Alexandre Torgue , Rob Herring , Mark Rutland , , , Loic Pallardy , "Gerald Baeza" , Patrice Chotard , "Kamel Kholti" CC: Benjamin Gaignard Subject: [PATCH v1 2/3] ARM: dts: stm32: add cec pins to stm32mp157c Date: Tue, 24 Apr 2018 09:54:08 +0200 Message-ID: <1524556449-5262-3-git-send-email-yannick.fertre@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1524556449-5262-1-git-send-email-yannick.fertre@st.com> References: <1524556449-5262-1-git-send-email-yannick.fertre@st.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.201.23.68] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2018-04-24_01:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds cec support on stm32mp157c eval board. Signed-off-by: Yannick Fertre --- arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi index 6f044100..67b0349 100644 --- a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi @@ -14,6 +14,15 @@ ranges = <0 0x50002000 0xa400>; pins-are-numbered; + cec_pins_a: cec@0 { + pins { + pinmux = ; + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + gpioa: gpio@50002000 { gpio-controller; #gpio-cells = <2>; -- 1.9.1