Received: by 10.192.165.148 with SMTP id m20csp4739875imm; Tue, 24 Apr 2018 07:41:35 -0700 (PDT) X-Google-Smtp-Source: AIpwx4937AmZtA/sX8T5Mfwl96c+YFY2V4nIB7/avvWe1oVcg3qFx9/hGDVQ6SrVNfgyGiBJ6Eco X-Received: by 10.98.233.11 with SMTP id j11mr24136606pfh.205.1524580895606; Tue, 24 Apr 2018 07:41:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1524580895; cv=none; d=google.com; s=arc-20160816; b=zjUccUEHIJ1+asbuAgR0aSJ8/jBEqSMDMfWWpxZBDQRPXQQguSl9Av7EZy5y0c+ogJ tvT/NI1AZz7oFp+6BHQg7QWEh56jXWg3tnter77nnUEIXztv9ZvZvKMqxpwHc+kN/Mpw TMa1RW3OCU3dRCvsHu0ETmZ58NWNp8Wd4oFmBs6NQ0+hV2Mp3UzhpkMxfMOpHtjs6diV nRcTSKFpZ4/8nFSKnkR902js2G5Asefw4bmMFFXpM31mIMJ0w+lq4zYMVarZ+gTh7qCb cVzmUZw3EbBcSsIxv95QN8kRJFTtz4XIIJHgjNsTt1q+b8e0xnPbW5R4vHoVn1GmUWe8 XmeA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:user-agent:in-reply-to :content-disposition:mime-version:references:message-id:subject:cc :to:from:date:arc-authentication-results; bh=sigWA7uHvbLYX7U1tRNfDPmNLgk+i6oc5ICn18ZZk68=; b=LWgvOw2PMc4L2YEtBgoY+iHbr3nufOvZMflYv4/vlS4DsR/VNBxnXrmgzhtiXeQJwj SEeGmeAQFxWPfhMVJNoI/S79gLunkwvACCDdJ9VSkwyN0aUOG3dxmZYSiUL6YAefVBiP +fVwkQI+z0aj75O5FepPsoxjn5ARDJavg5ELNj3q2gjcTltDhRVwSNp+n5F1pmVeCDVQ Qqk8U2BskeEW7k/Si7wEnhM4DSQyvFztxRjqqgXBh4V3OpNvquv1a7X3IGctrsIBe28S j0ZA2chOcxeS0aAu+NRwKnwvgcXHO+qa5wnugnHFICyxovaxuUbngfkSttYxhn6+fwZP C0dQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y23si1991164pff.177.2018.04.24.07.41.21; Tue, 24 Apr 2018 07:41:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753274AbeDXOjO (ORCPT + 99 others); Tue, 24 Apr 2018 10:39:14 -0400 Received: from mail-ot0-f196.google.com ([74.125.82.196]:41453 "EHLO mail-ot0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753039AbeDXOjK (ORCPT ); Tue, 24 Apr 2018 10:39:10 -0400 Received: by mail-ot0-f196.google.com with SMTP id t1-v6so1612550oth.8; Tue, 24 Apr 2018 07:39:09 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=sigWA7uHvbLYX7U1tRNfDPmNLgk+i6oc5ICn18ZZk68=; b=M9b85XQHcUxr1ymRd5PCDgu2rJR/iE9nh2KiiqSmTKmwTdSH3sTUNpkG6qz045mMvJ otznnSV2/yMicqtJ5I1SIdWFD8RYXRwZno2NJNOuVclRwf38xN1zIRBsgPiInNskuhrg YgqrERPrIe9WFaPHNwzJ3DWCfDSya7LswfcJcGGpmFEcFjnfn7NYYuMXnzSyS3dA36W4 ZMVHnF8wkyhFVf6P3jKlgUP3hADC+eMu10Kh2xdzTvBxGjgZT8+H0zZ5Vn88YB23Zf+m rF57cDeNSYYwnYJ+joLh4UZMnDdJkRB6VFIxJQ+rB795mssiNBoS/ibDnlrFTGrdLoXz ceMw== X-Gm-Message-State: ALQs6tAoGhkup9vgvMvN1oWro/F0DYJqW4ABZvqxjKIJUAN1+0CyE+hn iL2HkjICGa50Lxx/AR9tEA== X-Received: by 2002:a9d:3e07:: with SMTP id a7-v6mr4737821otd.150.1524580748659; Tue, 24 Apr 2018 07:39:08 -0700 (PDT) Received: from localhost (216-188-254-6.dyn.grandenetworks.net. [216.188.254.6]) by smtp.gmail.com with ESMTPSA id p72-v6sm9202353oie.33.2018.04.24.07.39.07 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 24 Apr 2018 07:39:08 -0700 (PDT) Date: Tue, 24 Apr 2018 09:39:07 -0500 From: Rob Herring To: sean.wang@mediatek.com Cc: mturquette@baylibre.com, sboyd@kernel.org, airlied@linux.ie, matthias.bgg@gmail.com, mark.rutland@arm.com, devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v1 2/4] dt-bindings: clock: mediatek: add g3dsys bindings Message-ID: <20180424143907.eewrpzdmkhhux3lb@rob-hp-laptop> References: <4b5d243d33433f83874359794b796d4228574714.1524044917.git.sean.wang@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4b5d243d33433f83874359794b796d4228574714.1524044917.git.sean.wang@mediatek.com> User-Agent: NeoMutt/20170609 (1.8.3) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Apr 18, 2018 at 06:24:54PM +0800, sean.wang@mediatek.com wrote: > From: Sean Wang > > Add bindings to g3dsys providing necessary clock and reset control to > Mali-450. > > Signed-off-by: Sean Wang > --- > .../bindings/arm/mediatek/mediatek,g3dsys.txt | 30 ++++++++++++++++++++++ > 1 file changed, 30 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt > > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt > new file mode 100644 > index 0000000..ff2d70c > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt > @@ -0,0 +1,30 @@ > +MediaTek g3dsys controller > +============================ > + > +The MediaTek g3dsys controller provides various clocks and reset controller to > +the GPU. > + > +Required Properties: > + > +- compatible: Should be: > + - "mediatek,mt2701-g3dsys", "syscon": > + for MT2701 SoC > + - "mediatek,mt7623-ethsys", "mediatek,mt2701-g3dsys", "syscon": > + for MT7623 SoC ethsys? > +- #clock-cells: Must be 1 > +- #reset-cells: Must be 1 > + > +The ethsys controller uses the common clk binding from > +Documentation/devicetree/bindings/clock/clock-bindings.txt > +The available clocks are defined in dt-bindings/clock/mt*-clk.h. > + > +Example: > + > +g3dsys: clock-controller@13000000 { > + compatible = "mediatek,mt7623-g3dsys", > + "mediatek,mt2701-g3dsys", > + "syscon"; > + reg = <0 0x13000000 0 0x200>; > + #clock-cells = <1>; > + #reset-cells = <1>; > +}; > -- > 2.7.4 >