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[209.132.180.67]) by mx.google.com with ESMTP id y6si11290719pgv.520.2018.04.24.08.00.59; Tue, 24 Apr 2018 08:01:15 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=LYOPoBzC; dkim=pass header.i=@codeaurora.org header.s=default header.b=EA989Xrc; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934439AbeDXNdW (ORCPT + 99 others); Tue, 24 Apr 2018 09:33:22 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:48964 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933338AbeDXNdQ (ORCPT ); Tue, 24 Apr 2018 09:33:16 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 2A9646034F; Tue, 24 Apr 2018 13:33:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1524576795; bh=Ub8NMeDljKq4ubmtQM+hR7u7mQwMrB3uCrocf3dyy/Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LYOPoBzCuD/JTX+ro9l5sO3fqVgSs7OVfLwakmaTj3h/z5G+jDrQWafXbuZ8dcbQg Bw+nFBORdSDRetn+5ee/VZ1BSrKm7omPeeT49vULw5YY6fIODmo0GbsrqDlugM5lYE vv73nQbyEc02ZxDtQ06uQpa8D7E38da0vBZSq7qs= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from anischal-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: anischal@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 931DE607E1; Tue, 24 Apr 2018 13:33:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1524576794; bh=Ub8NMeDljKq4ubmtQM+hR7u7mQwMrB3uCrocf3dyy/Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EA989XrcJPP0ikZzaadHlzx7qvf8adR4HCwmDN4Sqw2fD9UeJgWw5UkErjXQh0p3v LW5s5N2nq56hzw3sB8JpzS1O/qT55w1+U65lO6/N6r6GFo19Y5zgc6x/qmq8ZNd/92 ExF1X/EUqgH3hOV/GCpljOtBIf/LZiMPORjSL704= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 931DE607E1 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=anischal@codeaurora.org From: Amit Nischal To: Stephen Boyd , Michael Turquette Cc: Andy Gross , David Brown , Rajendra Nayak , Odelu Kukatla , Taniya Das , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Amit Nischal Subject: [PATCH 1/2] dt-bindings: clock: Introduce QCOM Video clock bindings Date: Tue, 24 Apr 2018 19:02:50 +0530 Message-Id: <1524576771-31096-2-git-send-email-anischal@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1524576771-31096-1-git-send-email-anischal@codeaurora.org> References: <1524576771-31096-1-git-send-email-anischal@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add device tree bindings for video clock controller for Qualcomm Technology Inc's SoCs. Signed-off-by: Amit Nischal --- .../devicetree/bindings/clock/qcom,videocc.txt | 18 ++++++++++++++++ include/dt-bindings/clock/qcom,videocc-sdm845.h | 25 ++++++++++++++++++++++ 2 files changed, 43 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,videocc.txt create mode 100644 include/dt-bindings/clock/qcom,videocc-sdm845.h diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.txt b/Documentation/devicetree/bindings/clock/qcom,videocc.txt new file mode 100644 index 0000000..1c23b41 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,videocc.txt @@ -0,0 +1,18 @@ +Qualcomm Video Clock & Reset Controller Binding +----------------------------------------------- + +Required properties : +- compatible : shall contain "qcom,videocc-sdm845" +- reg : shall contain base register location and length +- #clock-cells : shall contain 1 +- #reset-cells : shall contain 1 +- #power-domain-cells : shall contain 1 + +Example: + videocc: qcom,videocc@ab00000 { + compatible = "qcom,videocc-sdm845"; + reg = <0xab00000 0x10000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; diff --git a/include/dt-bindings/clock/qcom,videocc-sdm845.h b/include/dt-bindings/clock/qcom,videocc-sdm845.h new file mode 100644 index 0000000..f5f7599 --- /dev/null +++ b/include/dt-bindings/clock/qcom,videocc-sdm845.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. */ + +#ifndef _DT_BINDINGS_CLK_MSM_VIDEO_CC_SDM845_H +#define _DT_BINDINGS_CLK_MSM_VIDEO_CC_SDM845_H + +#define VIDEO_CC_APB_CLK 0 +#define VIDEO_CC_AT_CLK 1 +#define VIDEO_CC_QDSS_TRIG_CLK 2 +#define VIDEO_CC_QDSS_TSCTR_DIV8_CLK 3 +#define VIDEO_CC_VCODEC0_AXI_CLK 4 +#define VIDEO_CC_VCODEC0_CORE_CLK 5 +#define VIDEO_CC_VCODEC1_AXI_CLK 6 +#define VIDEO_CC_VCODEC1_CORE_CLK 7 +#define VIDEO_CC_VENUS_AHB_CLK 8 +#define VIDEO_CC_VENUS_CLK_SRC 9 +#define VIDEO_CC_VENUS_CTL_AXI_CLK 10 +#define VIDEO_CC_VENUS_CTL_CORE_CLK 11 +#define VIDEO_PLL0 12 + +#define VENUS_GDSC 0 +#define VCODEC0_GDSC 1 +#define VCODEC1_GDSC 2 + +#endif -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation