Received: by 10.192.165.148 with SMTP id m20csp4810068imm; Tue, 24 Apr 2018 08:45:23 -0700 (PDT) X-Google-Smtp-Source: AIpwx4/Y+mA42G4QULJso09jOIoEt5o5IvZLbc3a3Pz9H+kDUgFaFysZyaZs50RD6Wf0CcQnyThN X-Received: by 10.99.50.134 with SMTP id y128mr21269037pgy.419.1524584723886; Tue, 24 Apr 2018 08:45:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1524584723; cv=none; d=google.com; s=arc-20160816; b=MaW25GsvSlVAE8KLxsQtSQsSDDgSkQFiWHXC6H3Kz9SQF0B5i9Xp5qDhEEc5G6i0Mp W9xzQ9zpaww7Hgcxm+iHA1uu+nQLNjDjBsiagO+u6zB6F20MsidE/nXISTjmi1++dC5V XjKDwvjjcMZPzKoDbY+O4Zwr4QZ7kIti1azgqdWhgIL4mLAARG/dLNje7s2Jib0CZFrx t5n70mp3t8SJFkOWtIHHJuRBxCKKbHV2jomyF5B4f6MR65d1gBFUA/06KL/PedU2Kdsh ghySD+uVr1oR4U8GRl6itDzPY0M3TN7rOvKrAzRR/bZvGsU2/dZu4jLZ40y20xzZlD4v PPbg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:content-transfer-encoding :references:in-reply-to:date:cc:to:from:subject:message-id :arc-authentication-results; bh=91IPwa5XDHk9QIMP4zliQzw0bZHgPCx5XiWHe/jFenI=; b=mFIsG6PU+d/ZCBXgamXUC5cZ2gupfcE4k9rcVNNIcvnG7AhIPkCHzRHUFn6qDaFW1D M34ui5RasLIcDwFXPfwueJPiLv9I3nxj96lX92r5wCRflDWdJAgra2ltRhbYq+DhNHAZ tZueYnUecF6gLlc8etq+4r1+Gk+Pe3SOGwyILkfOs3srLsu4BuHFNtgUTDvaBLwYw7Ni EBl/hg0VvePMDZRcRYsgBoiBMBQL5EGaqhoyCbGRmyX4pvVEBKOQ9tKfwhWHtCldjbEi fa4TvWiI4MXFAl6uN9OHbx5ECUSYfFNzwzTIQ87CcBZ8ZS3L5LvAFz9Fuu/XaZWdJX9H QTSw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p11-v6si16927791plo.276.2018.04.24.08.45.09; Tue, 24 Apr 2018 08:45:23 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751445AbeDXPnd (ORCPT + 99 others); Tue, 24 Apr 2018 11:43:33 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:55216 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1750868AbeDXPn3 (ORCPT ); Tue, 24 Apr 2018 11:43:29 -0400 X-UUID: 8c3025185e4843fd91c0f697ab3acd20-20180424 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1690201113; Tue, 24 Apr 2018 23:43:24 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Tue, 24 Apr 2018 23:43:22 +0800 Received: from [172.21.77.33] (172.21.77.33) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Tue, 24 Apr 2018 23:43:22 +0800 Message-ID: <1524584602.12322.16.camel@mtkswgap22> Subject: Re: [PATCH v1 3/4] clk: mediatek: add g3dsys support for MT2701 and MT7623 From: Sean Wang To: Rob Herring CC: , , , , , , , , , , Date: Tue, 24 Apr 2018 23:43:22 +0800 In-Reply-To: <20180424144009.b66sxo3okjvsr4yc@rob-hp-laptop> References: <96dc02879c10388c2efa08b1cf33b77f938908ee.1524044917.git.sean.wang@mediatek.com> <20180424144009.b66sxo3okjvsr4yc@rob-hp-laptop> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.2.3-0ubuntu6 Content-Transfer-Encoding: 7bit MIME-Version: 1.0 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 2018-04-24 at 09:40 -0500, Rob Herring wrote: > On Wed, Apr 18, 2018 at 06:24:55PM +0800, sean.wang@mediatek.com wrote: > > From: Sean Wang > > > > Add clock driver support for g3dsys on MT2701 and MT7623, which is > > providing essential clock gate and reset controller to Mali-450. > > > > Signed-off-by: Sean Wang > > --- > > drivers/clk/mediatek/Kconfig | 6 ++ > > drivers/clk/mediatek/Makefile | 1 + > > drivers/clk/mediatek/clk-mt2701-g3d.c | 95 +++++++++++++++++++++++++++++++ > > > include/dt-bindings/clock/mt2701-clk.h | 4 ++ > > include/dt-bindings/reset/mt2701-resets.h | 3 + > > These below in the binding patch. > Thanks, I will split them out in the next version. > > 5 files changed, 109 insertions(+) > > create mode 100644 drivers/clk/mediatek/clk-mt2701-g3d.c