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[209.132.180.67]) by mx.google.com with ESMTP id b19si11559424pfh.358.2018.04.24.23.09.52; Tue, 24 Apr 2018 23:10:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=lW5vIAKt; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751301AbeDYGIv (ORCPT + 99 others); Wed, 25 Apr 2018 02:08:51 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:54788 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750968AbeDYGIt (ORCPT ); Wed, 25 Apr 2018 02:08:49 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id w3P67h7b005385; Wed, 25 Apr 2018 01:07:43 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1524636463; bh=Ep9XBAdvkLTefltb3t61ahDb5/UEe1GUpvEykjraLEQ=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=lW5vIAKtzv/SbiXV2SIPcLtsslQ5YNYdtipScqyBDJeJk9kvJjVVG6QbYL+B6kzvL 5UeOfrIHnaTlN0WqnRsS5eOm2/vnlnwGfiK07k90tLptRFAd6OAO6P5bJgDYgo8vlG xMdfxmA3OidRx0zwQnBMVwL6LfLkQdausJXKgotE= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w3P67hcN023468; Wed, 25 Apr 2018 01:07:43 -0500 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Wed, 25 Apr 2018 01:07:43 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Wed, 25 Apr 2018 01:07:43 -0500 Received: from [172.24.190.172] (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w3P67bBa011224; Wed, 25 Apr 2018 01:07:37 -0500 Subject: Re: [PATCH v5 12/44] clk: davinci: Add platform information for TI DA850 PSC To: David Lechner , Stephen Boyd , Bartosz Golaszewski CC: Michael Turquette , linux-clk , devicetree , Linux ARM , Stephen Boyd , Rob Herring , Mark Rutland , Kevin Hilman , Adam Ford , Linux Kernel Mailing List References: <1515377863-20358-1-git-send-email-david@lechnology.com> <1515377863-20358-13-git-send-email-david@lechnology.com> <69bc0848-0698-b936-96a3-2257a5e27809@ti.com> <57f2182e-09b4-2cab-5602-9d0e029495be@ti.com> <152303318048.143116.2883441215887455211@swboyd.mtv.corp.google.com> <48c8531f-8cd9-a9f8-9c38-cbc4c921c4c9@lechnology.com> From: Sekhar Nori Message-ID: Date: Wed, 25 Apr 2018 11:37:36 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tuesday 24 April 2018 09:41 PM, David Lechner wrote: > On 04/24/2018 03:28 AM, Sekhar Nori wrote: >> On Monday 23 April 2018 08:29 PM, David Lechner wrote: >>> On 04/06/2018 11:46 AM, Stephen Boyd wrote: >>>> Quoting Sekhar Nori (2018-04-06 02:37:03) >>>>> >>>>> Can you please check that and confirm there is no issue with genpd and >>>>> using CLK_OF_DECLARE() to initialize clocks? >>>>> >>>>> Unless you report an issue back, or Mike and Stephen have ideas about >>>>> how to handle the dependency between PSC/PLL derived timer clock >>>>> initialization and and timer_probe(), I think we need to move back to >>>>> using CLK_OF_DECLARE(). >>>> >>>> In such a case, please use the hybrid approach where the clks required >>>> for the clockevent and/or clocksource are registered in the early >>>> CLK_OF_DECLARE path but the rest of the clks get registered with a >>>> proper platform device and driver. There are examples of this approach >>>> on other platforms already. >>>> >>> >>> I looked at this a bit last week, but I didn't come up with any approach >>> that I was happy with. It seems like it would be nice to just register >>> the absolute minimum clocks needed. On DA8XX, that would just be the >>> PLL0 >>> AUXCLK. On most of the other SoCs, it would be the PLL AUXCLK plus one >>> LPSC clock. The AUXCLKs are easy because they are just a simple gate >>> from the oscillator. The LPSC clocks are a bit more tricky because they >>> have a complex sequence for turning on. Furthermore, on DM646X, we need >>> the whole PLL up to SYSCLK3 plus one LPSC clock, so things get a bit >>> messy there. >> >> Things might change in the context of work being done here by Bartosz >> for converting clocks to early platform devices. >> >> But, keeping that development aside for a moment: I think this means the >> PLLs and PSCs need to be CLK_OF_DECLARE(). What we can have as platform >> devices are clocks that are not in the path to get timer clock working >> (like CFGCHIP clocks). > > CLK_OF_DECLARE() only matters on DA850. None of the other SoCs use device Thats true today, but lets not make the assumption that none of the other DaVinci SoCs will gain DT support ever. We don't want churn in CCF support once someone tries to add DT support for other platforms. I already have people using DM365 in mainline, for example. > tree. And on DA850, the timer0 clock is just the PLL0 AUXCLK, so PSCs can> still be platform devices there. And in fact, one of the PSC clocks on > DA850 depends on async3, which is a CFGCHIP clock, so if we made the PSCs > CLK_OF_DECLARE(), then we also have to make at least the async3 CFGCHIP > clock CLK_OF_DECLARE(). But, like I said, I think that can be avoided by > leaving the PSC clocks as a platform device on DA850 (and DA830). Okay, I did not realize that there is a dependency between CFGCHIP clk and PSC too. > For everything else, we need the legacy board file equivalent of > CLK_OF_DECLARE(), which is basically what I had here in v5 of the > series. Yeah. I did not realize the dependency with timer when platform devices were suggested. Sorry. > > So, if we want this to keep moving before the if/when of Bartosz's > early platform device stuff, I'm thinking that I will make the PLL After looking at feedback to Bartosz's series, and the fact that previous attempts at doing the same thing were rejected, I think there is benefit in keeping CCF support moving independent Bartosz's work. Otherwise, we have no chance of getting anything merged for v4.18. Early initialization of clocks and dependency with timer is a pretty common theme across SoCs. As and when a better way to support is found, I am sure DaVinci can be converted over along with rest of the devices. > and PSC drivers loadable with or without a platform device and let > each SoC pick which one it should use. This sounds flexible. We have to see how the patches look. But I would caution against adding a lot of dead code. If there is no way some of the clocks will be useful as platform device, I see no point of supporting them as such just in anticipation. Thanks, Sekhar