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[209.132.180.67]) by mx.google.com with ESMTP id e188si15404999pfe.103.2018.04.25.03.06.03; Wed, 25 Apr 2018 03:06:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@ffwll.ch header.s=google header.b=K0h3EUiE; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751981AbeDYKEj (ORCPT + 99 others); Wed, 25 Apr 2018 06:04:39 -0400 Received: from mail-wm0-f49.google.com ([74.125.82.49]:38764 "EHLO mail-wm0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751725AbeDYKEe (ORCPT ); Wed, 25 Apr 2018 06:04:34 -0400 Received: by mail-wm0-f49.google.com with SMTP id i3so5743298wmf.3 for ; Wed, 25 Apr 2018 03:04:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=sender:date:from:to:cc:subject:message-id:mail-followup-to :references:mime-version:content-disposition:in-reply-to:user-agent; bh=qSlksoxjcWcbJL5iBNvBFn9tkQfrswkETKdMKNXIZ+Y=; b=K0h3EUiE91E2Ttu9jIfvHcciTmXXcjcFbyl8OcNDB3VomdDoRoSzoPcN5T1UMPkxSk f83+WB9eruTFQJe3P6tEDLJHdVrebSE4YEk+In6Vi1b4LSPpaXNFzI+iCGAho9MLyUMq bUxCsY1cZ0W31Dbq3D1mdhMMP4/7FGxE/qvr0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:date:from:to:cc:subject:message-id :mail-followup-to:references:mime-version:content-disposition :in-reply-to:user-agent; bh=qSlksoxjcWcbJL5iBNvBFn9tkQfrswkETKdMKNXIZ+Y=; b=NP6k/l7H+xqqlkOSkk6d9TritSiDoHOSYEKyPjZaWgOewb8GvDDbaN9SMo3qhp8DlY EmCe6JYGRVN3y2tvkEIMPcPOg0Dyv7x9z8loMqcuSCZARGRrPz1GHI+xpxUBaLJOg+Pp O1/WVnwqmSAtinZsmisjmVUM9B+mprXT/pn+UQHTWY7An1qn8wld99q5kA0WvSS/ur+l YtiFz2PyAO118gitU8hUa3YvZsquvwi5FwYI7f8yOWrC1ogIEVgo8QbK2nxcUKoreGGE ITMh/YBriBzNsoXMn+kIE1b53F5Z8zjTEQpSMkJkX0WaYNfKmQ9l1jH9eGN1iP5CuUdg WLog== X-Gm-Message-State: ALQs6tC/mrY6PCGqdUpKjE7pzwBK3/OX3G4VX/3QVDupQPt3EOosDquZ gQR0Z73yVQWla05LqDb/YYDjvQ== X-Received: by 10.80.129.164 with SMTP id 33mr38106245ede.199.1524650672817; Wed, 25 Apr 2018 03:04:32 -0700 (PDT) Received: from phenom.ffwll.local ([2a02:168:5635:0:39d2:f87e:2033:9f6]) by smtp.gmail.com with ESMTPSA id j89sm10258418edd.37.2018.04.25.03.04.31 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 25 Apr 2018 03:04:31 -0700 (PDT) Date: Wed, 25 Apr 2018 12:04:29 +0200 From: Daniel Vetter To: Christoph Hellwig Cc: Thierry Reding , Daniel Vetter , Christian =?iso-8859-1?Q?K=F6nig?= , "moderated list:DMA BUFFER SHARING FRAMEWORK" , Linux Kernel Mailing List , amd-gfx list , Jerome Glisse , dri-devel , Dan Williams , Logan Gunthorpe , "open list:DMA BUFFER SHARING FRAMEWORK" , iommu@lists.linux-foundation.org, linux-arm-kernel@lists.infradead.org Subject: Re: noveau vs arm dma ops Message-ID: <20180425100429.GR25142@phenom.ffwll.local> Mail-Followup-To: Christoph Hellwig , Thierry Reding , Christian =?iso-8859-1?Q?K=F6nig?= , "moderated list:DMA BUFFER SHARING FRAMEWORK" , Linux Kernel Mailing List , amd-gfx list , Jerome Glisse , dri-devel , Dan Williams , Logan Gunthorpe , "open list:DMA BUFFER SHARING FRAMEWORK" , iommu@lists.linux-foundation.org, linux-arm-kernel@lists.infradead.org References: <20180420124625.GA31078@infradead.org> <20180420152111.GR31310@phenom.ffwll.local> <20180424184847.GA3247@infradead.org> <20180425054855.GA17038@infradead.org> <20180425064335.GB28100@infradead.org> <20180425074151.GA2271@ulmo> <20180425085439.GA29996@infradead.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20180425085439.GA29996@infradead.org> X-Operating-System: Linux phenom 4.15.0-1-amd64 User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Apr 25, 2018 at 01:54:39AM -0700, Christoph Hellwig wrote: > [discussion about this patch, which should have been cced to the iommu > and linux-arm-kernel lists, but wasn't: > https://www.spinics.net/lists/dri-devel/msg173630.html] > > On Wed, Apr 25, 2018 at 09:41:51AM +0200, Thierry Reding wrote: > > > API from the iommu/dma-mapping code. Drivers have no business poking > > > into these details. > > > > The interfaces that the above patch uses are all EXPORT_SYMBOL_GPL, > > which is rather misleading if they are not meant to be used by drivers > > directly. > > The only reason the DMA ops are exported is because get_arch_dma_ops > references (or in case of the coherent ones used to reference). We > don't let drivers assign random dma ops. > > > > > > Thierry, please resend this with at least the iommu list and > > > linux-arm-kernel in Cc to have a proper discussion on the right API. > > > > I'm certainly open to help with finding a correct solution, but the > > patch above was purposefully terse because this is something that I > > hope we can get backported to v4.16 to unbreak Nouveau. Coordinating > > such a backport between ARM and DRM trees does not sound like something > > that would help getting this fixed in v4.16. > > Coordinating the backport of a trivial helper in the arm tree is not > the end of the world. Really, this cowboy attitude is a good reason > why graphics folks have such a bad rep. You keep poking into random > kernel internals, don't talk to anoyone and then complain if people > are upset. This shouldn't be surprising. Not really agreeing on the cowboy thing. The fundamental problem is that the dma api provides abstraction that seriously gets in the way of writing a gpu driver. Some examples: - We never want bounce buffers, ever. dma_map_sg gives us that, so there's hacks to fall back to a cache of pages allocated using dma_alloc_coherent if you build a kernel with bounce buffers. - dma api hides the cache flushing requirements from us. GPUs love non-snooped access, and worse give userspace control over that. We want a strict separation between mapping stuff and flushing stuff. With the IOMMU api we mostly have the former, but for the later arch maintainers regularly tells they won't allow that. So we have drm_clflush.c. - dma api hides how/where memory is allocated. Kinda similar problem, except now for CMA or address limits. So either we roll our own allocators and then dma_map_sg (and pray it doesn't bounce buffer), or we use dma_alloc_coherent and then grab the sgt to get at the CMA allocations because that's the only way. Which sucks, because we can't directly tell CMA how to back off if there's some way to make CMA memory available through other means (gpus love to hog all of memory, so we have shrinkers and everything). For display drivers the dma api mostly works, until you start sharing buffers with other devices. So from our perspective it looks fairly often that core folks just don't want to support gpu use-cases, so we play a bit more cowboy and get things done some other way. Since this has been going on for years now we often don't even bother to start a discussion first, since it tended to go nowhere useful. -Daniel > > Granted, this issue could've been caught with a little more testing, but > > in retrospect I think it would've been a lot better if ARM_DMA_USE_IOMMU > > was just enabled unconditionally if it has side-effects that platforms > > don't opt in to but have to explicitly opt out of. > > Agreed on that count. Please send a patch. -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch