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[209.132.180.67]) by mx.google.com with ESMTP id a1-v6si11675101plt.39.2018.04.25.10.47.15; Wed, 25 Apr 2018 10:47:29 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=hVWqgJZ9; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756114AbeDYRol (ORCPT + 99 others); Wed, 25 Apr 2018 13:44:41 -0400 Received: from mail-wm0-f53.google.com ([74.125.82.53]:55859 "EHLO mail-wm0-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754654AbeDYRof (ORCPT ); Wed, 25 Apr 2018 13:44:35 -0400 Received: by mail-wm0-f53.google.com with SMTP id a8so8587565wmg.5; Wed, 25 Apr 2018 10:44:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=YVoyRJf73mRX4k6gODdNLrW+HMd9t/SwgIwCs+gD56g=; b=hVWqgJZ9HtbX7XIeccQQtE6xMRrmt8r+BDEoY1bs4rmL/Hj8Zwmy/YGguDyjFm5gmI 77I8B6Xe/2J64BcX8Bjlt2LP07NuMUt2sWJwER1DFQv7mPSi4LIi0uE1rx9Un4HXckbk EIQLxQ825rx3yYctL4pKqvQtj54LQumJBp3salK7FrU50G4Is1CEb+IaA0U/uyBKmyzt K8i+A/3KUO5pCth+l4HvlLgVdj3/BLBY+851HAuRutiboSxprUd9z4stxKpJT9UDTr+n uKCYERGCtuVriCeIv0afKzcy304MNQGY4/CIEm/gSBrbi4pt34KJqVQSPw+YjRmBcIme FhmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=YVoyRJf73mRX4k6gODdNLrW+HMd9t/SwgIwCs+gD56g=; b=hIaOFTAREHVxaVCH2Ru8c3xAvma5Rqeb+ZHo3fOxC+0GbF0kS4QsBS3eGKPLDTALH8 hHU/Z+0yWg5BXQ67F8arGoZ6OnFFWiqyPh7ixeLejNxDExtxK3S4MNtnRfpYsCKOUEBs eIav8RozRrnnGzcxTPLlM09R8gsnrMdyz+aI94hnVz1aGGPOVcCTYgp9EdeeZZM7c/V6 fWJwOAw/yU72/gxJMWhoL7aG/6hBpbqsjNqVfEr1l/nXygWpQRdUBsrBm6jsln2jkIv/ SbEblTSoQRhZqLcWn3yzGecX3GO2hKqeuB5NUAUxk6WPvDeRK8+RawJp0lbbDObUrLzt y2uA== X-Gm-Message-State: ALQs6tDD3aKAfd6i9yHkOPs+uLgLZxJ1F01JaqE49HPtrPKuVyOnxVMo lpUIZIdT5gYTRytNN9drd2xXm6P/ZqJb+zplLSw= X-Received: by 10.28.197.205 with SMTP id v196mr1852916wmf.16.1524678274414; Wed, 25 Apr 2018 10:44:34 -0700 (PDT) MIME-Version: 1.0 Received: by 10.223.175.76 with HTTP; Wed, 25 Apr 2018 10:44:33 -0700 (PDT) In-Reply-To: <20180425064118.GA28100@infradead.org> References: <3e17afc5-7d6c-5795-07bd-f23e34cf8d4b@gmail.com> <20180420101755.GA11400@infradead.org> <20180420124625.GA31078@infradead.org> <20180420152111.GR31310@phenom.ffwll.local> <20180424184847.GA3247@infradead.org> <20180425054855.GA17038@infradead.org> <20180425064118.GA28100@infradead.org> From: Alex Deucher Date: Wed, 25 Apr 2018 13:44:33 -0400 Message-ID: Subject: Re: [Linaro-mm-sig] [PATCH 4/8] dma-buf: add peer2peer flag To: Christoph Hellwig Cc: Daniel Vetter , Linux Kernel Mailing List , dri-devel , "moderated list:DMA BUFFER SHARING FRAMEWORK" , Jerome Glisse , amd-gfx list , Dan Williams , Logan Gunthorpe , =?UTF-8?Q?Christian_K=C3=B6nig?= , "open list:DMA BUFFER SHARING FRAMEWORK" Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Apr 25, 2018 at 2:41 AM, Christoph Hellwig wrote: > On Wed, Apr 25, 2018 at 02:24:36AM -0400, Alex Deucher wrote: >> > It has a non-coherent transaction mode (which the chipset can opt to >> > not implement and still flush), to make sure the AGP horror show >> > doesn't happen again and GPU folks are happy with PCIe. That's at >> > least my understanding from digging around in amd the last time we had >> > coherency issues between intel and amd gpus. GPUs have some bits >> > somewhere (in the pagetables, or in the buffer object description >> > table created by userspace) to control that stuff. >> >> Right. We have a bit in the GPU page table entries that determines >> whether we snoop the CPU's cache or not. > > I can see how that works with the GPU on the same SOC or SOC set as the > CPU. But how is that going to work for a GPU that is a plain old PCIe > card? The cache snooping in that case is happening in the PCIe root > complex. I'm not a pci expert, but as far as I know, the device sends either a snooped or non-snooped transaction on the bus. I think the transaction descriptor supports a no snoop attribute. Our GPUs have supported this feature for probably 20 years if not more, going back to PCI. Using non-snooped transactions have lower latency and faster throughput compared to snooped transactions. Alex