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[209.132.180.67]) by mx.google.com with ESMTP id g13si14575746pgq.69.2018.04.25.23.27.48; Wed, 25 Apr 2018 23:28:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752902AbeDZG0l (ORCPT + 99 others); Thu, 26 Apr 2018 02:26:41 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:1942 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751477AbeDZG0j (ORCPT ); Thu, 26 Apr 2018 02:26:39 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Wed, 25 Apr 2018 23:26:21 -0700 Received: from HQMAIL108.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Wed, 25 Apr 2018 23:26:37 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Wed, 25 Apr 2018 23:26:37 -0700 Received: from BGMAIL102.nvidia.com (10.25.59.11) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 26 Apr 2018 06:26:38 +0000 Received: from [192.168.100.20] (10.19.65.191) by bgmail102.nvidia.com (10.25.59.11) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 26 Apr 2018 06:26:34 +0000 Subject: Re: [PATCH] net: phy: marvell: clear wol event before setting it To: Jisheng Zhang CC: Andrew Lunn , Florian Fainelli , "David S. Miller" , , , Jingju Hou References: <20180419160232.519d15be@xhacker.debian> <20180419121801.GC17888@lunn.ch> <4273f766-a017-b336-7d14-a28901d274b9@nvidia.com> <20180426141508.6660a633@xhacker.debian> From: Bhadram Varka Message-ID: Date: Thu, 26 Apr 2018 11:56:33 +0530 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: <20180426141508.6660a633@xhacker.debian> X-Originating-IP: [10.19.65.191] X-ClientProxiedBy: BGMAIL104.nvidia.com (10.25.59.13) To bgmail102.nvidia.com (10.25.59.11) Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 7bit Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On 4/26/2018 11:45 AM, Jisheng Zhang wrote: > Hi, > > On Thu, 26 Apr 2018 11:10:21 +0530 Bhadram Varka wrote: > >> Hi, >> >> On 4/19/2018 5:48 PM, Andrew Lunn wrote: >>> On Thu, Apr 19, 2018 at 04:02:32PM +0800, Jisheng Zhang wrote: >>>> From: Jingju Hou >>>> >>>> If WOL event happened once, the LED[2] interrupt pin will not be >>>> cleared unless reading the CSISR register. So clear the WOL event >>>> before enabling it. >>>> >>>> Signed-off-by: Jingju Hou >>>> Signed-off-by: Jisheng Zhang >>>> --- >>>> drivers/net/phy/marvell.c | 9 +++++++++ >>>> 1 file changed, 9 insertions(+) >>>> >>>> diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c >>>> index c22e8e383247..b6abe1cbc84b 100644 >>>> --- a/drivers/net/phy/marvell.c >>>> +++ b/drivers/net/phy/marvell.c >>>> @@ -115,6 +115,9 @@ >>>> /* WOL Event Interrupt Enable */ >>>> #define MII_88E1318S_PHY_CSIER_WOL_EIE BIT(7) >>>> >>>> +/* Copper Specific Interrupt Status Register */ >>>> +#define MII_88E1318S_PHY_CSISR 0x13 >>>> + >>>> /* LED Timer Control Register */ >>>> #define MII_88E1318S_PHY_LED_TCR 0x12 >>>> #define MII_88E1318S_PHY_LED_TCR_FORCE_INT BIT(15) >>>> @@ -1393,6 +1396,12 @@ static int m88e1318_set_wol(struct phy_device *phydev, >>>> if (err < 0) >>>> goto error; >>>> >>>> + /* If WOL event happened once, the LED[2] interrupt pin >>>> + * will not be cleared unless reading the CSISR register. >>>> + * So clear the WOL event first before enabling it. >>>> + */ >>>> + phy_read(phydev, MII_88E1318S_PHY_CSISR); >>>> + >>> Hi Jisheng >>> >>> The problem with this is, you could be clearing a real interrupt, link >>> down/up etc. If interrupts are in use, i think the normal interrupt >>> handling will clear the WOL interrupt? So can you make this read >>> conditional on !phy_interrupt_is_valid()? >> So this will clear WoL interrupt bit from Copper Interrupt status register. >> >> How about clearing WoL status (Page 17, register 17) for every WOL event ? >> > This is already properly done by setting MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS > in m88e1318_set_wol() This part of the code executes only when we enable WOL through ethtool (ethtool -s eth0 wol g) Lets say once WOL enabled through magic packet - HW generates WOL interrupt once magic packet received. The problem that I see here is that for the next immediate magic packet I don't see WOL interrupt generated by the HW. I need to explicitly clear WOL status for HW to generate WOL interrupt.