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[209.132.180.67]) by mx.google.com with ESMTP id c23-v6si18476975plk.245.2018.04.25.23.52.12; Wed, 25 Apr 2018 23:52:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ac9nv6NU; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753708AbeDZGug (ORCPT + 99 others); Thu, 26 Apr 2018 02:50:36 -0400 Received: from mail-wr0-f193.google.com ([209.85.128.193]:38444 "EHLO mail-wr0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753554AbeDZGuc (ORCPT ); Thu, 26 Apr 2018 02:50:32 -0400 Received: by mail-wr0-f193.google.com with SMTP id h3-v6so55559629wrh.5 for ; Wed, 25 Apr 2018 23:50:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:content-transfer-encoding:in-reply-to :user-agent; bh=GFEHWnfZk0DHdVJ5xcK7/VAEu62Vd//RdZhrHN0S9w4=; b=ac9nv6NU5SxmQN8SEV3dqliCyHw2+3LZWXBsHWc054JEb5mtDVi99eeEx582FT4hXy vRYNKWcamwu3BNtA/8tE8g3W20upUpmMms7SOWQp1rc5ib0Gnib/hvX7d/C/8NpSIh9L 9lZzOgkjebYdCIY4KQqaBW0DGhMFBmb+AFzAw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to:user-agent; bh=GFEHWnfZk0DHdVJ5xcK7/VAEu62Vd//RdZhrHN0S9w4=; b=ebaPS7Dt4Ls/YlKDBGCjPdTWnTizP+6qDyBfhiBCD8rMNkZjl2Wxs97CdD79hQbtOn UWp3cmNCWbXnv3wIgXLrxOhf3C9N+k9TIH4V0EgL1U2ghff8BVxofS2/qarh81yEbUZj k8TPdpTI2QQUy/6D7pT3+TLuF356/wJFl8llMPq5YGbo0CT4fS2b2gdThscc/79/Q7Pn 5AtCyfrDe4ZSYKya0PYgHm0D6ba+CCT3p2sWvemc87P0yIZQ9TK9dUCiT8HfomBRh2MH wvscWTKRprVqP5aukKTK/sbXBlo0Q20Ad5ct0OI0KNJb2HiRH2x8qilDjOdna3fq4MH5 24Tg== X-Gm-Message-State: ALQs6tCWWhaFYAbhl6uMWont2iQn0HMbzAiu1pNleAOwaRrW5X4xlOlX RbQ2QznA9QA6n7ThSgrRbA7LEA== X-Received: by 2002:adf:9bcd:: with SMTP id e13-v6mr1773905wrc.240.1524725431616; Wed, 25 Apr 2018 23:50:31 -0700 (PDT) Received: from dell ([2.27.167.55]) by smtp.gmail.com with ESMTPSA id q34-v6sm18547969wrb.27.2018.04.25.23.50.29 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 25 Apr 2018 23:50:30 -0700 (PDT) Date: Thu, 26 Apr 2018 07:50:28 +0100 From: Lee Jones To: Javier Arteaga Cc: Linus Walleij , Dan O'Donovan , Andy Shevchenko , Mika Westerberg , Heikki Krogerus , Jacek Anaszewski , Pavel Machek , linux-gpio@vger.kernel.org, linux-leds@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [RFC PATCH RESEND 3/3] pinctrl: upboard: Add UP2 pinctrl and gpio driver Message-ID: <20180426065028.fvdf7ke5va2kacmv@dell> References: <20180421085009.28773-1-javier@emutex.com> <20180421085009.28773-4-javier@emutex.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20180421085009.28773-4-javier@emutex.com> User-Agent: NeoMutt/20170609 (1.8.3) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, 21 Apr 2018, Javier Arteaga wrote: > The UP2 board features a Raspberry Pi compatible pin header (HAT) and a > board-specific expansion connector (EXHAT). Both expose assorted > functions from either the SoC (such as GPIO, I2C, SPI, UART...) or other > on-board devices (ADC, FPGA IP blocks...). > > These lines are routed through an on-board FPGA. The platform controller > in its stock firmware provides register fields to change: > > - Line enable (FPGA pins enabled / high impedance) > - Line direction (SoC driven / FPGA driven) > > To enable using SoC GPIOs on the pin header, this arrangement requires > both configuring the platform controller, and updating the SoC pad > registers in sync. > > Add a frontend pinctrl/GPIO driver that registers a new set of GPIO > lines for the header pins. When these are requested, the driver > propagates this request to the backend SoC pinctrl/GPIO driver by > grabbing a GPIO descriptor for the matching SoC GPIO line. The needed > mapping for this is retrieved via ACPI properties. > > Signed-off-by: Javier Arteaga > --- [...] > > drivers/mfd/upboard.c | 1 + > drivers/pinctrl/Kconfig | 13 + > drivers/pinctrl/Makefile | 1 + > drivers/pinctrl/pinctrl-upboard.c | 523 ++++++++++++++++++++++++++++++ > 4 files changed, 538 insertions(+) > create mode 100644 drivers/pinctrl/pinctrl-upboard.c > > diff --git a/drivers/mfd/upboard.c b/drivers/mfd/upboard.c > index 6e4767e4dc41..35111981dfdf 100644 > --- a/drivers/mfd/upboard.c > +++ b/drivers/mfd/upboard.c > @@ -132,6 +132,7 @@ static struct upboard_led_data upboard_up2_led_data[] = { > }; > > static const struct mfd_cell upboard_up2_mfd_cells[] = { > + { .name = "upboard-pinctrl" }, > UPBOARD_LED_CELL(upboard_up2_led_data, 0), > UPBOARD_LED_CELL(upboard_up2_led_data, 1), > UPBOARD_LED_CELL(upboard_up2_led_data, 2), Please made this a separate patch. There aren't any build dependencies between the files. -- Lee Jones [李琼斯] Linaro Services Technical Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog