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[209.132.180.67]) by mx.google.com with ESMTP id p21si10949588pgv.401.2018.04.26.09.23.15; Thu, 26 Apr 2018 09:23:29 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756780AbeDZQUc (ORCPT + 99 others); Thu, 26 Apr 2018 12:20:32 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:52635 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1756820AbeDZQTX (ORCPT ); Thu, 26 Apr 2018 12:19:23 -0400 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w3QFsRlJ020603; Thu, 26 Apr 2018 18:18:39 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2hfv6f3t3q-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 26 Apr 2018 18:18:39 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 8DCB431; Thu, 26 Apr 2018 16:18:38 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas23.st.com [10.75.90.46]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 64A445147; Thu, 26 Apr 2018 16:18:38 +0000 (GMT) Received: from SAFEX1HUBCAS21.st.com (10.75.90.44) by SAFEX1HUBCAS23.st.com (10.75.90.46) with Microsoft SMTP Server (TLS) id 14.3.361.1; Thu, 26 Apr 2018 18:18:38 +0200 Received: from lmecxl0923.lme.st.com (10.48.0.237) by Webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.361.1; Thu, 26 Apr 2018 18:18:37 +0200 From: Ludovic Barre To: Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring CC: Maxime Coquelin , Alexandre Torgue , Gerald BAEZA , Loic PALLARDY , , , , "Ludovic Barre" Subject: [PATCH 00/11] irqchip: stm32: add exti support for stm32mp157c Date: Thu, 26 Apr 2018 18:18:23 +0200 Message-ID: <1524759514-12392-1-git-send-email-ludovic.Barre@st.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.48.0.237] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2018-04-26_06:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ludovic Barre Exti controller has been differently integrated on stm32mp1 SoC. A parent irq has only one external interrupt Vs stm32f4: one parent irq can have some external interrupts. On stm32mp1 hierachy domain could be used. Handlers are call by parent, each parent interrupt could be masked and unmasked according to the needs. Introduces chips/host/driver data structure to support different stm32 exti controllers variant and regroup common functions which could be reused by variants. Ludovic Barre (10): irqchip: stm32: checkpatch fix irqchip: stm32: add falling pending register support irqchip: stm32: add suspend support irqchip: stm32: add host and driver data structures irqchip: stm32: prepare common functions irqchip: stm32: add stm32mp1 support with hierarchy domain irqchip: stm32: add suspend/resume support for hierarchy domain pinctrl: stm32: add irq_eoi for stm32gpio irqchip ARM: dts: stm32: add exti support for stm32mp157c ARM: dts: stm32: add exti support to stm32mp157 pinctrl radek (1): irqchip: stm32: Optimizes and cleans up stm32-exti irq_domain .../interrupt-controller/st,stm32-exti.txt | 3 + arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 4 + arch/arm/boot/dts/stm32mp157c.dtsi | 7 + drivers/irqchip/irq-stm32-exti.c | 683 ++++++++++++++++++--- drivers/pinctrl/stm32/pinctrl-stm32.c | 13 +- 5 files changed, 612 insertions(+), 98 deletions(-) -- 2.7.4