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[209.132.180.67]) by mx.google.com with ESMTP id h3-v6si81814pld.137.2018.04.26.17.24.34; Thu, 26 Apr 2018 17:24:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@lechnology.com header.s=default header.b=jZUsnhLW; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757431AbeD0AXG (ORCPT + 99 others); Thu, 26 Apr 2018 20:23:06 -0400 Received: from vern.gendns.com ([206.190.152.46]:46339 "EHLO vern.gendns.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757291AbeD0ASp (ORCPT ); Thu, 26 Apr 2018 20:18:45 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lechnology.com; s=default; h=References:In-Reply-To:Message-Id:Date:Subject :Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=chOQpK60D0VKLfJHf23otOL4eKXQ/0z/mzkt+EUOXW4=; b=jZUsnhLW/MnWwkqie0JjZWbeT Tn8J9/XMFK4C2K4ll+9wJEll/nrf9avo1jqKm+Y4/Bp+UkDQzfBx5BLXO61co/Ojvk5OAwzM6db1t qGvfW6hmW7XEkpz2iqmPheVy5bky1QkqnevkcCQkP+Zm4wzdbwjXLYSM96liKyIYIiHbW9j0PYrRb P5VavEQvS6YuTgcGby3zljVy9i18E95sRtVpP4a8Qs/aGtwhrB9faiqUV+HbYgI1vHDdnMVFLy8uC Qr2zT4Pz/2ZAaVmeAj1JF9q4KfZplJ2NyERsJB+bw9hvrvw7hU5Ow4STs02znP19OF7+tZSQ1CBQ5 jaeuSCToA==; Received: from 108-198-5-147.lightspeed.okcbok.sbcglobal.net ([108.198.5.147]:39016 helo=freyr.lechnology.com) by vern.gendns.com with esmtpsa (TLSv1.2:ECDHE-RSA-AES128-GCM-SHA256:128) (Exim 4.89_1) (envelope-from ) id 1fBr63-000iph-Hy; Thu, 26 Apr 2018 20:18:43 -0400 From: David Lechner To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Sekhar Nori , Kevin Hilman , Bartosz Golaszewski , Adam Ford , linux-kernel@vger.kernel.org, David Lechner Subject: [PATCH v9 15/27] ARM: davinci: switch to common clock framework Date: Thu, 26 Apr 2018 19:17:33 -0500 Message-Id: <20180427001745.4116-16-david@lechnology.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180427001745.4116-1-david@lechnology.com> References: <20180427001745.4116-1-david@lechnology.com> X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - vern.gendns.com X-AntiAbuse: Original Domain - vger.kernel.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - lechnology.com X-Get-Message-Sender-Via: vern.gendns.com: authenticated_id: davidmain+lechnology.com/only user confirmed/virtual account not confirmed X-Authenticated-Sender: vern.gendns.com: davidmain@lechnology.com X-Source: X-Source-Args: X-Source-Dir: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This switches ARCH_DAVINCI to use the common clock framework. The legacy clock code in arch/arm/mach-davinci/ is no longer used. New drivers in drivers/clk/davinci/ are used instead. A few macros had to be moved to prevent compilation errors. Signed-off-by: David Lechner --- v9 changes: - none v8 changes: - none v7 changes: - s/compile/compilation and space instead of tab - add PM_GENERIC_DOMAINS dependencies v6 changes: - clean up indent on Common objects section arch/arm/Kconfig | 5 ++++- arch/arm/mach-davinci/Makefile | 4 ++-- arch/arm/mach-davinci/clock.h | 4 ---- arch/arm/mach-davinci/davinci.h | 4 ++++ arch/arm/mach-davinci/psc.h | 2 -- 5 files changed, 10 insertions(+), 9 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a7f8e7f4b88f..a57ad13810c8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -609,13 +609,16 @@ config ARCH_S3C24XX config ARCH_DAVINCI bool "TI DaVinci" select ARCH_HAS_HOLES_MEMORYMODEL - select CLKDEV_LOOKUP + select COMMON_CLK select CPU_ARM926T select GENERIC_ALLOCATOR select GENERIC_CLOCKEVENTS select GENERIC_IRQ_CHIP select GPIOLIB select HAVE_IDE + select PM_GENERIC_DOMAINS if PM + select PM_GENERIC_DOMAINS_OF if PM && OF + select RESET_CONTROLLER select USE_OF select ZONE_DMA help diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index 4e8178050027..8725d8bea567 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -5,8 +5,8 @@ # # Common objects -obj-y := time.o clock.o serial.o psc.o \ - usb.o common.o sram.o aemif.o +obj-y := time.o serial.o usb.o \ + common.o sram.o aemif.o obj-$(CONFIG_DAVINCI_MUX) += mux.o diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h index d7894d5aaa25..2d058568e004 100644 --- a/arch/arm/mach-davinci/clock.h +++ b/arch/arm/mach-davinci/clock.h @@ -12,10 +12,6 @@ #ifndef __ARCH_ARM_DAVINCI_CLOCK_H #define __ARCH_ARM_DAVINCI_CLOCK_H -#define DAVINCI_PLL1_BASE 0x01c40800 -#define DAVINCI_PLL2_BASE 0x01c40c00 -#define MAX_PLL 2 - /* PLL/Reset register offsets */ #define PLLCTL 0x100 #define PLLCTL_PLLEN BIT(0) diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h index fa99197d36f9..db4c95ef4d5c 100644 --- a/arch/arm/mach-davinci/davinci.h +++ b/arch/arm/mach-davinci/davinci.h @@ -35,6 +35,10 @@ #include #include +#define DAVINCI_PLL1_BASE 0x01c40800 +#define DAVINCI_PLL2_BASE 0x01c40c00 +#define DAVINCI_PWR_SLEEP_CNTRL_BASE 0x01c41000 + #define DAVINCI_SYSTEM_MODULE_BASE 0x01c40000 #define SYSMOD_VDAC_CONFIG 0x2c #define SYSMOD_VIDCLKCTL 0x38 diff --git a/arch/arm/mach-davinci/psc.h b/arch/arm/mach-davinci/psc.h index 8af9f09fc10c..b58707cf7033 100644 --- a/arch/arm/mach-davinci/psc.h +++ b/arch/arm/mach-davinci/psc.h @@ -27,8 +27,6 @@ #ifndef __ASM_ARCH_PSC_H #define __ASM_ARCH_PSC_H -#define DAVINCI_PWR_SLEEP_CNTRL_BASE 0x01C41000 - /* Power and Sleep Controller (PSC) Domains */ #define DAVINCI_GPSC_ARMDOMAIN 0 #define DAVINCI_GPSC_DSPDOMAIN 1 -- 2.17.0