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[209.132.180.67]) by mx.google.com with ESMTP id h10si517226pfh.278.2018.04.26.22.01.03; Thu, 26 Apr 2018 22:01:19 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=bB0sMTHG; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751543AbeD0E76 (ORCPT + 99 others); Fri, 27 Apr 2018 00:59:58 -0400 Received: from mail-pf0-f173.google.com ([209.85.192.173]:43567 "EHLO mail-pf0-f173.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751140AbeD0E74 (ORCPT ); Fri, 27 Apr 2018 00:59:56 -0400 Received: by mail-pf0-f173.google.com with SMTP id j11so566897pff.10 for ; Thu, 26 Apr 2018 21:59:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=mime-version:content-transfer-encoding:to:from:in-reply-to:cc :references:message-id:user-agent:subject:date; bh=faxkLKNL2Hi6EU5COY5tiRYA1kz5htEubQcC1yMqhSo=; b=bB0sMTHGcd/uD09sEL7UAOliVzEthxLRI/2UCk9L6yfWtF+H3f3meuphHfcXbYxYc1 urj0nURJtcZJtdPd5xwCFZnQHNb8A6miFCD8x77oxa6JWjytBnDBtTW56GdmwZKbgAIB JYiDm4SSwve1GiyYurxgOU4BSyVhwcnM3MuYGs4OTATTnN9en+NXxL8kzpA6Kihy+MZp 3frESYggFssq8HVq6SJWtiKhcy7LNmvRceLmzz4wK3CH7RL2MJSEHyInzuWHhtApsE2w TeahhRQ/FPBBz8g30sit7flZZnjjuPqhxS1m6gxdYibr0qQTF9v5YQv857R5SmINDaCa AlKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:content-transfer-encoding:to:from :in-reply-to:cc:references:message-id:user-agent:subject:date; bh=faxkLKNL2Hi6EU5COY5tiRYA1kz5htEubQcC1yMqhSo=; b=rjkaJGH4kxODPkFGwHA8akcySZoNxPHvPA8nu4gpl/hrEPqv/riorN0FxMzQ2iv3Cz g74jzWDsSLdHQWMM2ToLJJC4SK/o47HqYBCZ1yAKfmfv5pT0Lyd6643fYpfkWIM0BX1K iA/A0s1Am1nxPuB0IdikjQ+8m1iKNZ1WfhM0T4377VGt+fFSp+tEotq8u5FP3i3D3Efq sH8uatZmkvVuEvSkd5mhrekd9Igl+4oqDzHoo44jBVrvZievP+nB6eldKBBvmwDQl7V5 K/Hxs2uvuSXY76Hrc47xJVSJ+WTZF6KQdzd2GX5/KDIKrugHsfFH9dWJFL3W0adglW4P D8Ug== X-Gm-Message-State: ALQs6tApAs6LHtltBIkMwZ59ezcOb8E76BGoxJznGOx8f3etV3zSIHMQ 1lAdPLSqQ0SVwaq41W/8bwhazA== X-Received: by 2002:a65:6410:: with SMTP id a16-v6mr808961pgv.75.1524805195622; Thu, 26 Apr 2018 21:59:55 -0700 (PDT) Received: from localhost ([2605:e000:151d:20c0:8449:622d:e18f:736b]) by smtp.gmail.com with ESMTPSA id m66sm771161pfb.82.2018.04.26.21.59.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 26 Apr 2018 21:59:54 -0700 (PDT) Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: Jerome Brunet , Stephen Boyd From: Michael Turquette In-Reply-To: <1517575828.3153.23.camel@baylibre.com> Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Russell King , Linus Walleij , Quentin Schulz , Kevin Hilman , Maxime Ripard References: <20171201215200.23523-1-jbrunet@baylibre.com> <151373031022.33554.13905466641279532222@resonance> <20171222021520.GO7997@codeaurora.org> <1517217778.3153.1.camel@baylibre.com> <20180201174307.GC23162@codeaurora.org> <1517575828.3153.23.camel@baylibre.com> Message-ID: <20180423182136.43156.94025@harbor.lan> User-Agent: alot/0.7 Subject: Re: [PATCH v5 00/10] clk: implement clock rate protection mechanism Date: Mon, 23 Apr 2018 11:21:36 -0700 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Quoting Jerome Brunet (2018-02-02 04:50:28) > On Thu, 2018-02-01 at 09:43 -0800, Stephen Boyd wrote: > > > > > Applied to clk-protect-rate, with the exception that I did not ap= ply > > > > > "clk: fix CLK_SET_RATE_GATE with clock rate protection" as it bre= aks > > > > > qcom clk code. > > > > > = > > > > > Stephen, do you plan to fix up the qcom clock code so that the > > > > > SET_RATE_GATE improvement can go in? > > > > > = > > > > = > > > > I started working on it a while back. Let's see if I can finish > > > > it off this weekend. > > > > = > > > = > > > Hi Stephen, > > > = > > > Have you been able find something to fix the qcom code regarding this= issue ? > > > = > > = > > This is what I have. I'm unhappy with a few things. First, I made > > a spinlock for each clk, which is overkill. Most likely, just a > > single spinlock is needed per clk-controller device. Second, I > > haven't finished off the branch/gate part, so gating/ungating of > > branches needs to be locked as well to prevent branches from > > turning on while rates change. And finally, the 'branches' list is > > duplicating a bunch of information about the child clks of an > > RCG, so it feels like we need a core framework API to enable and > > disable clks forcibly while remembering what is enabled/disabled > > or at least to walk the clk tree and call some function. > = > Looks similar to Mike's CCR idea ;) Giving clk provider drivers more control over the clocks that they provide is a similar concept, but the ancient ccr series dealt almost exclusively with set_rate and set_parent ops. > = > > = > > The spinlock per clk-controller is duplicating the regmap lock we > > already have, so we may want a regmap API to grab the lock, and > > then another regmap API to do reads/writes without grabbing the > > lock, and then finally release the lock with a regmap unlock API. > = > There is 'regsequence' for multiple write in a burst, but that's only if = you do > write only ... I suppose you are more in read/update/writeback mode, so it > probably does not help much. > = > Maybe we could extend regmap's regsequence, to do a sequence of > regmap_update_bits() ? > = > Another possibility could be to provide your own lock/unlock ops when > registering the regmap. With this, you might be able to supply your own s= pinlock > to regmap. This is already supported by regmap, would it help ? Stephen, was there ever an update on your end? This patch has been dangling for a while and I thought it was time to ping on it. Regards, Mike > = > > This part is mostly an optimization, but it would be nice to have > > so that multiple writes could be done in sequence. This way, the > > RCG code could do the special locking sequence and the branch > > code could do the fire and forget single bit update. > =20