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[209.132.180.67]) by mx.google.com with ESMTP id z9-v6si779173pgz.62.2018.04.27.00.54.05; Fri, 27 Apr 2018 00:54:19 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=VhWsssQZ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757588AbeD0Hwy (ORCPT + 99 others); Fri, 27 Apr 2018 03:52:54 -0400 Received: from mail-qt0-f180.google.com ([209.85.216.180]:34390 "EHLO mail-qt0-f180.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757171AbeD0Hww (ORCPT ); Fri, 27 Apr 2018 03:52:52 -0400 Received: by mail-qt0-f180.google.com with SMTP id m5-v6so1173468qti.1; Fri, 27 Apr 2018 00:52:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:sender:in-reply-to:references:from:date:message-id :subject:to:cc; bh=9hCR4FdpJAQQFCHKC0qBIYceVywu/uFGtYMqI+anffA=; b=VhWsssQZjWlnPLyUdD0w922rr3RjDnR6MXd9EYfRv4tPbhIrGyvPZswX36NoNKlp/u eQ51/j2+yU67tTBpr7BrdjDpyBJjTYBl0pjUEQgXbyH6KrXPz3wGaJ+WYLiCfVx8iNaB YiXquKFwIq6iE86WLUrbhj3YCVouI2YIbdBxpL5bJp8pMz7USUzMP+zNgbJCmqBCrtok dt0eA8Geg137w8hzumjdtvbYp72H9Yy5cGYZIVjZ27Rcy18nBlxS4C9siUycSxkDRk3b VZE+8/7D5V6BckkxYw0VHsAJFTErtzNkP7SZ0rqOIvuAz7H8oCVU/opfM5MSV3z2wMDy j85A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:sender:in-reply-to:references:from :date:message-id:subject:to:cc; bh=9hCR4FdpJAQQFCHKC0qBIYceVywu/uFGtYMqI+anffA=; b=WQ9aaRRhjpWqaHBtHw2CUGww9i2eRxlnUHauF2Ii8fF44Uwb3sc7Y+f5lh0WggsYDa 676Z2+mLJH9KMn6Fqr5ecxiXvDtpvI8PlrZdun1p7UqVm4vionem4hD1v/x/AVtRU0od AGl0+bhV7kZ/NMpg6HJwRxgUar41j2xWYnvawwlOzEJsEw7poeRW91g0s0tJiPAS3U/0 mtnTOcDDJHBGt9QzEHIfXLLSaXMVShw+aGCZSCHYulEXCZGYOpOcadNjodhxQDM3lS6U oV8ghZ+5TKHgfq9dCypjlPPyGJ2RpmK2lbpcI1EC6XkooUEoOaNlR8U0qBPMvGqGC9rg PaEw== X-Gm-Message-State: ALQs6tDD9amz5uz9M14++zOq3zqRTfLC5rOulB5CJj52yMwpktwk4adI Equsb9ZOuma6IqLcwTav+K12633yZJhZ6keqONw= X-Received: by 2002:a0c:bd06:: with SMTP id m6-v6mr1038673qvg.156.1524815571669; Fri, 27 Apr 2018 00:52:51 -0700 (PDT) MIME-Version: 1.0 Received: by 10.12.185.3 with HTTP; Fri, 27 Apr 2018 00:52:51 -0700 (PDT) In-Reply-To: <6d1f9114-f1d1-961f-4f36-74adff059dc3@lechnology.com> References: <20180426152920.21569-1-brgl@bgdev.pl> <20180426173151.GJ3094@brightrain.aerifal.cx> <6d1f9114-f1d1-961f-4f36-74adff059dc3@lechnology.com> From: Arnd Bergmann Date: Fri, 27 Apr 2018 09:52:51 +0200 X-Google-Sender-Auth: 29yabX5CDB7JI5xahR7T74qd6GE Message-ID: Subject: Re: [PATCH RFC PoC 0/2] platform: different approach to early platform drivers To: David Lechner Cc: Rich Felker , Bartosz Golaszewski , Sekhar Nori , Kevin Hilman , Michael Turquette , Stephen Boyd , Greg Kroah-Hartman , Rob Herring , Mark Rutland , Yoshinori Sato , Frank Rowand , "Rafael J . Wysocki" , Jarkko Sakkinen , Dmitry Torokhov , Arend van Spriel , Heikki Krogerus , Michal Suchanek , Jan Kiszka , Andy Shevchenko , Marc Zyngier , Peter Rosin , Linux ARM , Linux Kernel Mailing List , DTML , Bartosz Golaszewski Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Apr 27, 2018 at 4:28 AM, David Lechner wrote: > On 04/26/2018 12:31 PM, Rich Felker wrote: >> >> On Thu, Apr 26, 2018 at 05:29:18PM +0200, Bartosz Golaszewski wrote: >>> >>> From: Bartosz Golaszewski >>> >>> This is a follow to my series[1] the aim of which was to introduce device >>> tree >>> support for early platform devices. >>> >>> It was received rather negatively. Aside from using device tree to pass >>> implementation specific details to the system, two important concerns >>> were >>> raised: no probe deferral support and the fact that currently the early >>> devices >>> never get converted to actual platform drivers. This series is a >>> proof-of-concept that's trying to address those issues. >>> >>> The only user of the current version of early platform drivers is the >>> SuperH >>> architecture. If this series eventually gets merged, we could simply >>> replace >>> the other solution. >> >> >> Looking at a quick output of: >> >> grep -r -A10 early_devices[[] arch/sh/kernel/ >> >> it looks like all of the existing early platform devices are serial >> ports, clocks, and clocksources. The switch to device tree should pick >> them all up from CLK_OF_DECLARE, TIMER_OF_DECLARE, and >> EARLYCON_DECLARE. Until that's complete, the existing code works >> as-is. I don't see what problem you're trying to solve. > > > The problem for us is that clk maintainers don't want new drivers to use > CLK_OF_DECLARE and instead use platform devices. I have just written such > a new driver that is shared by 6 different SoCs. For some combinations of > SoCs and clocks, using a platform device is fine but on others we need to > register early, so the drivers now have to handle both cases, which is > kind of messy and fragile. If there is a generic way to register platform > devices early, then the code is simplified because we only have to handle > one method of registering the clocks instead of two. The early_platform code is certainly not a way to make things simpler, it just adds one more way of doing the same thing that OF_CLK_DECLARE already does. We removed the last early_platform users on ARM a few years ago, and I would hope to leave it like that. I haven't seen the discussion about your clock drivers, but I know that usually only a very small subset of the clocks on an SoC are needed that 'early', and you should use a regular platform driver for the rest. Can you elaborate on which devices need to access your clocks before you are able to initialize the clk driver through the regular platform_driver framework? Do any of these need complex interactions with the clk subsystem, or do you just need to ensure they are turned on? Arnd