Received: by 10.192.165.148 with SMTP id m20csp435822imm; Fri, 27 Apr 2018 01:16:26 -0700 (PDT) X-Google-Smtp-Source: AB8JxZp327XpKRvQiV8VNyamocgvHo2bHuggUwF1IpibxNmV8E+15/Z7QLY7ssqVLV/n9eGa9vG0 X-Received: by 2002:a63:345:: with SMTP id 66-v6mr1299045pgd.98.1524816986927; Fri, 27 Apr 2018 01:16:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1524816986; cv=none; d=google.com; s=arc-20160816; b=RBh83VBVEwz3VwxiaJLXyUNrqOmC9TmHthhjrKTkXolbCdtOlddZmuvjKR7gqD2Lfz eOy3PtDsBa4gLMEaY5pvWohxRnMZK15LjeeU/wT8HidDEpVwTHN+gV4ZaMOpjwwbS4AK K/uqmW/5XZeXSwEls3uT0TrSh9N7toLnJEOM7dz8To0TG7O983AuJhonAJP/Fvkhd+w+ 9vpQynEF1+QW+NEppP8QX+MhK577UDiRgoALiBUEtRRfM+EAJIQgtWL/pbwy+wRFxbZ/ MUqiADqQ3lzYaVGb8YpJDrfyhX0b8VRKc0H9DPbbGnl2zr1b+UcxuexmRjCFQwycL8Kp trKA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=9p61GgCsCvXEUq0XJIzMLelaZStj3DtJp1tnKVYCk0Q=; b=RifqsLC12PS6xEMh7O4E2TmelLYTQKgsZ/AALYRgo5Snpv5vwDdOSksC2hZOUNh68n 3B5Ai/JaftSjacEKMZImPnD/VR7GxLY/oMVSpdjZ7xl5rFl8JqxIwD8BmSXJk9jDMIBc yTaksyRRSgfVojnmQzNmo4rqtfsV6ftgS1nRU9NrgQE9k4KGsX/n+Jp8QM4V+Gh8eKOi m6Hy6iG9I2y0eQyKGj3VsqMUY8R1kPAexfbMM5LSCXNd68tgscNwEqoQPyi8EwAgbkNa 4fG+g4+LLD1KONFU2ibrxKc9fIWQniU5yp7zSS4t5liLkqlB3qqPMh38TBldszFCJXeW u3gg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g11si833481pfk.187.2018.04.27.01.16.12; Fri, 27 Apr 2018 01:16:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757701AbeD0IPF (ORCPT + 99 others); Fri, 27 Apr 2018 04:15:05 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:52899 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1757650AbeD0IPC (ORCPT ); Fri, 27 Apr 2018 04:15:02 -0400 X-UUID: ea93953e2edb49679cc78833dd920f65-20180427 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1763935348; Fri, 27 Apr 2018 16:14:57 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Fri, 27 Apr 2018 16:14:48 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Fri, 27 Apr 2018 16:14:48 +0800 From: To: , , , , , CC: , , , , , Sean Wang Subject: [PATCH v2 1/6] dt-bindings: gpu: mali-utgard: add mediatek,mt7623-mali compatible Date: Fri, 27 Apr 2018 16:14:42 +0800 Message-ID: <7ab060c2e9ef2b220fc62913b8936b706dfaf202.1524816502.git.sean.wang@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Sean Wang The MediaTek MT7623 SoC contains a Mali-450, so add a compatible for it and define its own vendor-specific properties. Reviewed-by: Rob Herring Signed-off-by: Sean Wang --- Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt index 99d1c0a..656068f 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt @@ -19,6 +19,7 @@ Required properties: + rockchip,rk3228-mali + rockchip,rk3328-mali + stericsson,db8500-mali + + mediatek,mt7623-mali - reg: Physical base address and length of the GPU registers @@ -89,6 +90,14 @@ to specify one more vendor-specific compatible, among: * interrupt-names and interrupts: + combined: combined interrupt of all of the above lines + - mediatek,mt7623-mali + Required properties: + * resets: phandle to the reset line for the GPU + * mediatek,larb: phandle pointed to the local arbiter used to control the + access to external memory on the SoC. + see Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt + for details + Example: mali: gpu@1c40000 { -- 2.7.4