Received: by 10.192.165.148 with SMTP id m20csp436404imm; Fri, 27 Apr 2018 01:17:12 -0700 (PDT) X-Google-Smtp-Source: AB8JxZrJV7GxwmeK9dFclPDfQ9ZaGE6htdg6IeuQ6eWIqOXqujTlwZQ2m8q4NqefRXbQdERNDgDW X-Received: by 2002:a17:902:322:: with SMTP id 31-v6mr1405279pld.122.1524817032102; Fri, 27 Apr 2018 01:17:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1524817032; cv=none; d=google.com; s=arc-20160816; b=mXjrlhQkZsnxqa6UgY6v9dueUTgpYIQb+qbXkV5lewD9f/ZlwloP++E++Ai1VVaiH0 q6LTXJGu6gMPMr1AyO4AYSVkHn+AIBEfWj+pEH00+w612mshf7wqOjRzr4oUgjXg0ot3 ZScmb5R3yYRUOk7c06sl/7TryZM4BRsb/lK4A82k81MoMI2yS/CCWRsODsWf09mr6gZk GDy0mlCmpYA1DPdKuAqoA1otP0XOJ1o57wNQRcJ1sH1+IiqOaDC35D+XXQZA+EtC7QUM bf+sMimIOVpK1/9PKuI13mQCZccg7CN7bZl2ieoLP1lvXe1OlWJ/U6CT3z979uDoPt+I 8Axw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=wkX9QpwA3XdXh6Y1ftJt+EA8YA4Ct624iFi88+RC6TM=; b=YmgwDkdqJzVJu7dx+nICfXb7Xjwsd8lawnSwJ+Ic8SgOkpmluVg+Sf3xOAF3EqSXbr z/GOYbtnjnrPRN22N4S6hYDZXylX9h0DomCpBunvARNyp3NUcdEzUtF0vJoEmBYPZrPB ehrRz+FqhE/yjBPSQ5ZO6kHQo+wWGpLpw20f76+eluB9Z1PaWh3Nvtewxk569B8LvfuX cH9kQXgv1F9ZAYww5OyAziuNlwS8D02s472Gc4hiXH/OLjLoq811AFemRxk8gHvcdtl0 IT5u/Gi9nmab1FXXGS13IA5A3zIl1LveWKPvhnUyfA7j0osoVFPXZdi6+w5Om4wZUgDR LWAA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u75si832976pfd.183.2018.04.27.01.16.58; Fri, 27 Apr 2018 01:17:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757761AbeD0IP3 (ORCPT + 99 others); Fri, 27 Apr 2018 04:15:29 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:44791 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1757640AbeD0IOz (ORCPT ); Fri, 27 Apr 2018 04:14:55 -0400 X-UUID: d26dcfc1b7b1449ab978df5b29a6c616-20180427 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1033501459; Fri, 27 Apr 2018 16:14:50 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Fri, 27 Apr 2018 16:14:49 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Fri, 27 Apr 2018 16:14:49 +0800 From: To: , , , , , CC: , , , , , Sean Wang Subject: [PATCH v2 4/6] dt-bindings: reset: mediatek: add entry for Mali-450 node to refer Date: Fri, 27 Apr 2018 16:14:45 +0800 Message-ID: X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Sean Wang Just add binding for a required reset referenced by Mali-450 on MT7623 or MT2701 SoC. Cc: devicetree@vger.kernel.org Signed-off-by: Sean Wang --- include/dt-bindings/reset/mt2701-resets.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/dt-bindings/reset/mt2701-resets.h b/include/dt-bindings/reset/mt2701-resets.h index 21deb54..50b7f06 100644 --- a/include/dt-bindings/reset/mt2701-resets.h +++ b/include/dt-bindings/reset/mt2701-resets.h @@ -87,4 +87,7 @@ #define MT2701_ETHSYS_GMAC_RST 23 #define MT2701_ETHSYS_PPE_RST 31 +/* G3DSYS resets */ +#define MT2701_G3DSYS_CORE_RST 0 + #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT2701 */ -- 2.7.4