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[209.132.180.67]) by mx.google.com with ESMTP id t6si865515pfg.114.2018.04.27.01.38.48; Fri, 27 Apr 2018 01:39:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=HVqXLN5k; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932344AbeD0Ihg (ORCPT + 99 others); Fri, 27 Apr 2018 04:37:36 -0400 Received: from fllnx210.ext.ti.com ([198.47.19.17]:40375 "EHLO fllnx210.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757548AbeD0Ihd (ORCPT ); Fri, 27 Apr 2018 04:37:33 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id w3R8Tqen009506; Fri, 27 Apr 2018 03:29:52 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1524817792; bh=BL+O4EhVL7NuTDd7pcSoymPRj1sujF2yVvhssuBEfOc=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=HVqXLN5kjntZapHbHzfJc+ukrYKHJom4+UEkhx7pzIFDKDa9g+KkhIeMkJ95FGK1l GLLuYnKazQA8/sid8R9UcJGC0Q8Avyg+R+vSAOWwgTBBiwrwCQuU2h0Whcrjf2vJwN YQi7eJ8d3bvatYX2XZv4IFcUx8eYE9ajQRogwwYQ= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w3R8TpWw009015; Fri, 27 Apr 2018 03:29:51 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Fri, 27 Apr 2018 03:29:51 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Fri, 27 Apr 2018 03:29:51 -0500 Received: from [172.24.190.172] (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w3R8TeQk028124; Fri, 27 Apr 2018 03:29:41 -0500 Subject: Re: [PATCH RFC PoC 0/2] platform: different approach to early platform drivers To: Arnd Bergmann , David Lechner CC: Rich Felker , Bartosz Golaszewski , Kevin Hilman , Michael Turquette , Stephen Boyd , Greg Kroah-Hartman , Rob Herring , Mark Rutland , Yoshinori Sato , Frank Rowand , "Rafael J . Wysocki" , Jarkko Sakkinen , Dmitry Torokhov , Arend van Spriel , Heikki Krogerus , Michal Suchanek , Jan Kiszka , Andy Shevchenko , Marc Zyngier , Peter Rosin , Linux ARM , Linux Kernel Mailing List , DTML , Bartosz Golaszewski References: <20180426152920.21569-1-brgl@bgdev.pl> <20180426173151.GJ3094@brightrain.aerifal.cx> <6d1f9114-f1d1-961f-4f36-74adff059dc3@lechnology.com> From: Sekhar Nori Message-ID: <6194511c-b649-8c02-7db0-3514bfb292f5@ti.com> Date: Fri, 27 Apr 2018 13:59:39 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Arnd, On Friday 27 April 2018 01:22 PM, Arnd Bergmann wrote: > On Fri, Apr 27, 2018 at 4:28 AM, David Lechner wrote: >> On 04/26/2018 12:31 PM, Rich Felker wrote: >>> >>> On Thu, Apr 26, 2018 at 05:29:18PM +0200, Bartosz Golaszewski wrote: >>>> >>>> From: Bartosz Golaszewski >>>> >>>> This is a follow to my series[1] the aim of which was to introduce device >>>> tree >>>> support for early platform devices. >>>> >>>> It was received rather negatively. Aside from using device tree to pass >>>> implementation specific details to the system, two important concerns >>>> were >>>> raised: no probe deferral support and the fact that currently the early >>>> devices >>>> never get converted to actual platform drivers. This series is a >>>> proof-of-concept that's trying to address those issues. >>>> >>>> The only user of the current version of early platform drivers is the >>>> SuperH >>>> architecture. If this series eventually gets merged, we could simply >>>> replace >>>> the other solution. >>> >>> >>> Looking at a quick output of: >>> >>> grep -r -A10 early_devices[[] arch/sh/kernel/ >>> >>> it looks like all of the existing early platform devices are serial >>> ports, clocks, and clocksources. The switch to device tree should pick >>> them all up from CLK_OF_DECLARE, TIMER_OF_DECLARE, and >>> EARLYCON_DECLARE. Until that's complete, the existing code works >>> as-is. I don't see what problem you're trying to solve. >> >> >> The problem for us is that clk maintainers don't want new drivers to use >> CLK_OF_DECLARE and instead use platform devices. I have just written such >> a new driver that is shared by 6 different SoCs. For some combinations of >> SoCs and clocks, using a platform device is fine but on others we need to >> register early, so the drivers now have to handle both cases, which is >> kind of messy and fragile. If there is a generic way to register platform >> devices early, then the code is simplified because we only have to handle >> one method of registering the clocks instead of two. > > The early_platform code is certainly not a way to make things simpler, > it just adds one more way of doing the same thing that OF_CLK_DECLARE > already does. We removed the last early_platform users on ARM a few > years ago, and I would hope to leave it like that. > > I haven't seen the discussion about your clock drivers, but I know that > usually only a very small subset of the clocks on an SoC are needed > that 'early', and you should use a regular platform driver for the rest. Its true that the subset is small, but they are either PLL bypass clocks or clocks derived out of the main clock gate controller on the Soc (DaVinci PSC). So we need some non-platform-device based initialization support in the two main clock drivers used on mach-davinci anyway. > Can you elaborate on which devices need to access your clocks before > you are able to initialize the clk driver through the regular platform_driver > framework? Do any of these need complex interactions with the clk > subsystem, or do you just need to ensure they are turned on? Its just the timer IP. There is no complex interaction, just need to ensure that the clock is registered with the framework and also switched on when there is a gate clock. The latest attempt by David for this was posted last night here: https://lkml.org/lkml/2018/4/26/1093 Thanks, Sekhar