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[209.132.180.67]) by mx.google.com with ESMTP id u131-v6si865152pgc.11.2018.04.27.01.57.00; Fri, 27 Apr 2018 01:57:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=lmWV6TSD; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932420AbeD0Izx (ORCPT + 99 others); Fri, 27 Apr 2018 04:55:53 -0400 Received: from mail-qt0-f193.google.com ([209.85.216.193]:38401 "EHLO mail-qt0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932282AbeD0Izv (ORCPT ); Fri, 27 Apr 2018 04:55:51 -0400 Received: by mail-qt0-f193.google.com with SMTP id z23-v6so1321170qti.5; Fri, 27 Apr 2018 01:55:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:sender:in-reply-to:references:from:date:message-id :subject:to:cc; bh=5QbK94HRzOP2gzF8faMvwXm5S8itdMKn4+kVaNFei8U=; b=lmWV6TSD+yXflNKZk1RaDq8aaD3xF0QFBjP/9BX4N6JhltVvkcV+i9sBBDDYw6/y3G 0yHawkdRy6nXTaqD+aD5Ttle485JoyKig3RBXY72VDNo65gg2v1qFyp3H02izxHNyNqY kEg0d1EXWwinsugm/owRQzZUMQBB8pzX6QD5wv0P5CWFp8jb8C51GvRpGTf+fKc49NO5 HqoSRSdjBbhrcCpAbCQEcWnVoLFNcBqYJ9AcTDMTmS3+JQcBW+ZuiGi5MmVQs/729wz1 KHHWgDvWVF3puA6A3kO2Ggh8QjpY4LLnB7TXoSU1PYCZoLwoeDTB2ucvu0qKFhBgBF5j qrPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:sender:in-reply-to:references:from :date:message-id:subject:to:cc; bh=5QbK94HRzOP2gzF8faMvwXm5S8itdMKn4+kVaNFei8U=; b=qPt+nwKPQYXrTmVMr5sxfq06u1FWPGbTtYuYso2ecBmhKfQxPz23djOuq4+Fv/YXD0 S4vo3MOCFXGocXZhbaqQceb0peGqsjqS1TpDe3agd0zljzsdKX9q8Q+1AYg1DrZKf8Sv rBjyqlomb1jlGvtQpRoDwMtr4nxyaDu43wEinqBqjOqyrgh8KOdnK46UKYfACATtxwKG WaHr08H5Gb5UKJ5uaKRAN3XXDikwsFqoG4nL92RGtl64SpCDYrR43JWGkxCk5ADBnLou tHBkL1/AQafKUEoo9xx4T6Q2GUSeZTHC0rK2wFQlIHJfq3N5mF2D2UY6PpgsgxUtCtUu C0bQ== X-Gm-Message-State: ALQs6tCys9BQse4Bb9d4Kb33YYtTjFuZEE1RZDtCJj2IeL4X4mpcRZf/ NPgxu+7LgnNmMkGMFHmzW5rCCpkiaZZKcThlWmM= X-Received: by 2002:ac8:119a:: with SMTP id d26-v6mr1105117qtj.389.1524819350963; Fri, 27 Apr 2018 01:55:50 -0700 (PDT) MIME-Version: 1.0 Received: by 10.12.185.3 with HTTP; Fri, 27 Apr 2018 01:55:50 -0700 (PDT) In-Reply-To: <6194511c-b649-8c02-7db0-3514bfb292f5@ti.com> References: <20180426152920.21569-1-brgl@bgdev.pl> <20180426173151.GJ3094@brightrain.aerifal.cx> <6d1f9114-f1d1-961f-4f36-74adff059dc3@lechnology.com> <6194511c-b649-8c02-7db0-3514bfb292f5@ti.com> From: Arnd Bergmann Date: Fri, 27 Apr 2018 10:55:50 +0200 X-Google-Sender-Auth: F2gS2lx9g9Ux2GPpOZBQoSttWTk Message-ID: Subject: Re: [PATCH RFC PoC 0/2] platform: different approach to early platform drivers To: Sekhar Nori Cc: David Lechner , Rich Felker , Bartosz Golaszewski , Kevin Hilman , Michael Turquette , Stephen Boyd , Greg Kroah-Hartman , Rob Herring , Mark Rutland , Yoshinori Sato , Frank Rowand , "Rafael J . Wysocki" , Jarkko Sakkinen , Dmitry Torokhov , Arend van Spriel , Heikki Krogerus , Michal Suchanek , Jan Kiszka , Andy Shevchenko , Marc Zyngier , Peter Rosin , Linux ARM , Linux Kernel Mailing List , DTML , Bartosz Golaszewski Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Apr 27, 2018 at 10:29 AM, Sekhar Nori wrote: > On Friday 27 April 2018 01:22 PM, Arnd Bergmann wrote: >> On Fri, Apr 27, 2018 at 4:28 AM, David Lechner wrote: >>> On 04/26/2018 12:31 PM, Rich Felker wrote: >> >> I haven't seen the discussion about your clock drivers, but I know that >> usually only a very small subset of the clocks on an SoC are needed >> that 'early', and you should use a regular platform driver for the rest. > > Its true that the subset is small, but they are either PLL bypass clocks > or clocks derived out of the main clock gate controller on the Soc > (DaVinci PSC). So we need some non-platform-device based initialization > support in the two main clock drivers used on mach-davinci anyway. > >> Can you elaborate on which devices need to access your clocks before >> you are able to initialize the clk driver through the regular platform_driver >> framework? Do any of these need complex interactions with the clk >> subsystem, or do you just need to ensure they are turned on? > > Its just the timer IP. There is no complex interaction, just need to > ensure that the clock is registered with the framework and also switched > on when there is a gate clock. > > The latest attempt by David for this was posted last night here: > > https://lkml.org/lkml/2018/4/26/1093 Ok, so the workaround in that series is to set up the timer clk manually in the SoC specific code (dm365_init_time etc) and register it to the clk subsystem, right? That seems to be a much more appropriate workaround than adding back early_platform devices. We can always try to do something better later, but for now I'm happy with that as a workaround. Please clarify: do we have to set up the clk registers for the timer here just because we can't rely on the bootloader to have it set up initially, or is there some other reason? I think what some other platforms do is to treat the timer clock as a fixed-rate clock that is not managed by the actual clk driver but is set up by uboot before we enter the kernel, and then the clk driver just makes sure it doesn't turn that clk off later. Arnd