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[209.132.180.67]) by mx.google.com with ESMTP id j123si1116552pfg.156.2018.04.27.05.04.24; Fri, 27 Apr 2018 05:04:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@synopsys.com header.s=mail header.b=aGKXYLKr; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=synopsys.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758081AbeD0MBZ (ORCPT + 99 others); Fri, 27 Apr 2018 08:01:25 -0400 Received: from smtprelay6.synopsys.com ([198.182.37.59]:36060 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757681AbeD0MAP (ORCPT ); Fri, 27 Apr 2018 08:00:15 -0400 Received: from mailhost.synopsys.com (mailhost1.synopsys.com [10.12.238.239]) by smtprelay.synopsys.com (Postfix) with ESMTP id D6D1F1E161C; Fri, 27 Apr 2018 14:00:12 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=synopsys.com; s=mail; t=1524830413; bh=emUsAuwaOnqg8sBsoWdrfkEHpKTpjYThidr4qi3JNsE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:In-Reply-To: References:From; b=aGKXYLKrsAL9cWgA3rOkAqUBYfYUkb4jOoPdWDvxBKaQMXBWJzt93vLtvTLrA6QCb eCggoQqd6PSghCDwKYiNP8ppQ9CArOp+iG4kTmWbMeyLcH/l77MOKBSxUoI+gdVk1x JdGi1EVjXskD+yh3W7yNQqM4CmCLdDXjd5MzfgLt8QObXAxXL7qGdDe0ADJWxChNYv fOFM1KbEgeU7j593qeU77kVd3wUbqw7MOmUqL2/K2300kavRcO3sF62Ee6YPBhvy1a BuXrjedK62Cp2cf6GJF/7QrsYvyj5JMy8IMtGbJ7KMjBmFU6We8qy7B35iC7Z3wj9K N+uRxLvsdTMwg== Received: from pt02.synopsys.com (pt02.internal.synopsys.com [10.107.23.240]) by mailhost.synopsys.com (Postfix) with ESMTP id 0866550BD; Fri, 27 Apr 2018 05:00:11 -0700 (PDT) Received: from UbuntuMate-64Bits.internal.synopsys.com (gustavo-e7480.internal.synopsys.com [10.107.25.102]) by pt02.synopsys.com (Postfix) with ESMTP id C94FB3E572; Fri, 27 Apr 2018 13:00:08 +0100 (WEST) From: Gustavo Pimentel To: bhelgaas@google.com, lorenzo.pieralisi@arm.com, Joao.Pinto@synopsys.com, jingoohan1@gmail.com, kishon@ti.com, robh+dt@kernel.org, mark.rutland@arm.com Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, gustavo.pimentel@synopsys.com Subject: [PATCH v8 6/9] PCI: dwc: Define maximum number of vectors Date: Fri, 27 Apr 2018 13:00:01 +0100 Message-Id: <66e6e2a103c576a9e7f65a416b452e9c3e782de3.1524829928.git.gustavo.pimentel@synopsys.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a callback to define the maximum number of vectors used by the RC. Since this is a parameter associated to each SoC IP setting, makes sense to be configurable and easily visible to future modifications. Set DesignWare driver vectors number maximum to 256. Signed-off-by: Gustavo Pimentel Acked-by: Joao Pinto Acked-by: Jingoo Han --- Change v1->v2: - Nothing changed, just to follow the patch set version. Change v2->v3: - Nothing changed, just to follow the patch set version. Changes v3->v4: - Nothing changed, just to follow the patch set version. Changes v4->v5: - Nothing changed, just to follow the patch set version. Changes v5->v6: - Nothing changed, just to follow the patch set version. Changes v6->v7: - Nothing changed, just to follow the patch set version. Changes v7->v8: - Patch description rework for an imperative verbal mode. drivers/pci/dwc/pcie-designware-plat.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/pci/dwc/pcie-designware-plat.c b/drivers/pci/dwc/pcie-designware-plat.c index efc315c..5937fed 100644 --- a/drivers/pci/dwc/pcie-designware-plat.c +++ b/drivers/pci/dwc/pcie-designware-plat.c @@ -48,8 +48,14 @@ static int dw_plat_pcie_host_init(struct pcie_port *pp) return 0; } +static void dw_plat_set_num_vectors(struct pcie_port *pp) +{ + pp->num_vectors = MAX_MSI_IRQS; +} + static const struct dw_pcie_host_ops dw_plat_pcie_host_ops = { .host_init = dw_plat_pcie_host_init, + .set_num_vectors = dw_plat_set_num_vectors, }; static int dw_plat_pcie_establish_link(struct dw_pcie *pci) -- 2.7.4