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[209.132.180.67]) by mx.google.com with ESMTP id o3-v6si1417603pls.498.2018.04.27.09.02.53; Fri, 27 Apr 2018 09:03:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758587AbeD0P6S (ORCPT + 99 others); Fri, 27 Apr 2018 11:58:18 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:43110 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758236AbeD0P6R (ORCPT ); Fri, 27 Apr 2018 11:58:17 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EF85015AD; Fri, 27 Apr 2018 08:58:16 -0700 (PDT) Received: from [10.1.206.73] (en101.cambridge.arm.com [10.1.206.73]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D508A3F487; Fri, 27 Apr 2018 08:58:14 -0700 (PDT) Subject: Re: [PATCH v2 08/17] kvm: arm/arm64: Prepare for VM specific stage2 translations From: Suzuki K Poulose To: Julien Grall , linux-arm-kernel@lists.infradead.org Cc: ard.biesheuvel@linaro.org, kvm@vger.kernel.org, marc.zyngier@arm.com, catalin.marinas@arm.com, punit.agrawal@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, kristina.martsenko@arm.com, pbonzini@redhat.com, kvmarm@lists.cs.columbia.edu References: <1522156531-28348-1-git-send-email-suzuki.poulose@arm.com> <1522156531-28348-9-git-send-email-suzuki.poulose@arm.com> <7f67fca2-b936-25d9-0fe8-aece1fadafdc@arm.com> <59fc0fe3-2c7e-b5ae-702b-0c21f0051c6b@arm.com> Message-ID: Date: Fri, 27 Apr 2018 16:58:13 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: <59fc0fe3-2c7e-b5ae-702b-0c21f0051c6b@arm.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 27/04/18 16:22, Suzuki K Poulose wrote: > On 26/04/18 14:35, Julien Grall wrote: >> Hi Suzuki, >> >> On 27/03/18 14:15, Suzuki K Poulose wrote: >>> Right now the stage2 page table for a VM is hard coded, assuming >>> an IPA of 40bits. As we are about to add support for per VM IPA, >>> prepare the stage2 page table helpers to accept the kvm instance >>> to make the right decision for the VM. No functional changes. > > >>> diff --git a/arch/arm/include/asm/kvm_arm.h b/arch/arm/include/asm/kvm_arm.h >>> index 3ab8b37..c3f1f9b 100644 >>> --- a/arch/arm/include/asm/kvm_arm.h >>> +++ b/arch/arm/include/asm/kvm_arm.h >>> @@ -133,8 +133,7 @@ >>>    * space. >>>    */ >>>   #define KVM_PHYS_SHIFT    (40) >>> -#define KVM_PHYS_SIZE    (_AC(1, ULL) << KVM_PHYS_SHIFT) >>> -#define KVM_PHYS_MASK    (KVM_PHYS_SIZE - _AC(1, ULL)) >> >> I assume you are moving them to kvm_mmu.h in order to match the arm64 side, right? If so, would not it make sense to make KVM_PHYS_SHIFT with it? >> >> [...] > > I am moving all the macros that depend on the "kvm" instance to kvm_mmu.h. > I will see if I can move the KVM_PHYS_SHIFT without much trouble. It looks like we can't do that easily. KVM_PHYS_SHIFT is used for KVM_T0SZ on arm, even though that can be simply hard coded to avoid the dependency on KVM_PHYS_SHIFT (like we did for arm64, T0SZ is defined to 24). I would leave it as it is to avoid the noise. Cheers Suzuki