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[209.132.180.67]) by mx.google.com with ESMTP id l22-v6si5245990pgn.74.2018.04.29.14.52.24; Sun, 29 Apr 2018 14:52:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=RC1Cuotm; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754391AbeD2VwE (ORCPT + 99 others); Sun, 29 Apr 2018 17:52:04 -0400 Received: from mail-vk0-f67.google.com ([209.85.213.67]:41812 "EHLO mail-vk0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754036AbeD2VwA (ORCPT ); Sun, 29 Apr 2018 17:52:00 -0400 Received: by mail-vk0-f67.google.com with SMTP id 131-v6so4081666vkf.8 for ; Sun, 29 Apr 2018 14:52:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=eXNGQN2HfBK1DebVCDUX3h2r2HNapBb1EDhBIbYqvu0=; b=RC1CuotmgCo/QZSH+0ypg3PYbi0rtGkysu/i3l6nJxEFYT9heXcwdEecWffKpjGQjs z3ZkcA7Pgc7LzJywpVC7TcMD/sP2jpYRGwlkAYsPlEhenw5CcMZMe5X5cmMNsvVh2xeT /98wVHgechuaJiW4jNTuwnfdMoUf6ei0+kv+Q= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=eXNGQN2HfBK1DebVCDUX3h2r2HNapBb1EDhBIbYqvu0=; b=rGjyfcYCnkW8p+bnqleV0Bhu1S+kVWNJHibMBjhx4UQnBLT/Q9hpNBnnY41kYl0IGq LdLcp7xwraNBNcwKXQUaBA1hxP0162ByDAXhH4p4wW67YamMOkQ+V7FGLi10J7D0KYDo VYsXSEv7Ng6dd7VP3K6wsBQff8RpWD0pVpisuAh5tRLwRAGNK76KqZ/iFNE3BvjvsU1M oEEhGxHcNwY3+4UjobLHT5xAsiGhVp07fV32YMn/jc2z/7usS+XM20dgPOy/nXPY2gwX BBqva6KUKcC2jVX8ls8P1FxdHn7D9Q5EnSURp7JUluZSPLmTswZFoZfTswd/9eyMgRnK Hm6A== X-Gm-Message-State: ALQs6tAnt6CBprnZq+WlVKfrZg+Hdj+GQlUOW/MhqQJf3S8wdFqSc834 RZbBp9DExZ96jg62+3/dddNv1s0vzl9N9qpz3G21ww== X-Received: by 2002:a1f:c5c5:: with SMTP id v188-v6mr7270446vkf.48.1525038719039; Sun, 29 Apr 2018 14:51:59 -0700 (PDT) MIME-Version: 1.0 References: <1524741374-13523-1-git-send-email-Vijendar.Mukunda@amd.com> <1524741374-13523-9-git-send-email-Vijendar.Mukunda@amd.com> In-Reply-To: <1524741374-13523-9-git-send-email-Vijendar.Mukunda@amd.com> From: Daniel Kurtz Date: Sun, 29 Apr 2018 21:51:48 +0000 Message-ID: Subject: Re: [PATCH 09/11] ASoC: AMD: Fix clocks in CZ DA7219 machine driver To: Vijendar.Mukunda@amd.com Cc: Akshu Agrawal , Liam Girdwood , Mark Brown , perex@perex.cz, tiwai@suse.com, Kuninori Morimoto , alexander.deucher@amd.com, weiyongjun1@huawei.com, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Apr 26, 2018 at 5:17 AM Vijendar Mukunda wrote: > From: Akshu Agrawal > System clock on the platform is 25Mhz and not 24Mhz. > PLL_OUT for da7219 codec to use DA7219_PLL_FREQ_OUT_98304 > as it is for 48KHz SR. > Signed-off-by: Akshu Agrawal > Signed-off-by: Vijendar Mukunda Reviewed-by: Daniel Kurtz > --- > sound/soc/amd/acp-da7219-max98357a.c | 5 ++--- > 1 file changed, 2 insertions(+), 3 deletions(-) > diff --git a/sound/soc/amd/acp-da7219-max98357a.c b/sound/soc/amd/acp-da7219-max98357a.c > index 6495eed..fa5ad5b 100644 > --- a/sound/soc/amd/acp-da7219-max98357a.c > +++ b/sound/soc/amd/acp-da7219-max98357a.c > @@ -39,8 +39,7 @@ > #include "../codecs/da7219.h" > #include "../codecs/da7219-aad.h" > -#define CZ_PLAT_CLK 24000000 > -#define MCLK_RATE 24576000 > +#define CZ_PLAT_CLK 25000000 > #define DUAL_CHANNEL 2 > static struct snd_soc_jack cz_jack; > @@ -63,7 +62,7 @@ static int cz_da7219_init(struct snd_soc_pcm_runtime *rtd) > } > ret = snd_soc_dai_set_pll(codec_dai, 0, DA7219_SYSCLK_PLL, > - CZ_PLAT_CLK, MCLK_RATE); > + CZ_PLAT_CLK, DA7219_PLL_FREQ_OUT_98304); > if (ret < 0) { > dev_err(rtd->dev, "can't set codec pll: %d\n", ret); > return ret; > -- > 2.7.4